llvm.org GIT mirror llvm / 3f63013
[CodeGen] Print global addresses as @foo in both MIR and debug output Work towards the unification of MIR and debug output by printing `@foo` instead of `<ga:@foo>`. Also print target flags in the MIR format since most of them are used on global address operands. Only debug syntax is affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320682 91177308-0d34-0410-b5e6-96231b3b80d8 Francis Visoiu Mistrih 2 years ago
11 changed file(s) with 172 addition(s) and 136 deletion(s). Raw diff Collapse all Expand all
238238 /// called to check this.
239239 static void printSubregIdx(raw_ostream &OS, uint64_t Index,
240240 const TargetRegisterInfo *TRI);
241 /// Print operand target flags.
242 static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
241243
242244 /// Print the MachineOperand to \p os.
243245 /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
160160 void printIRValueReference(const Value &V);
161161 void printStackObjectReference(int FrameIndex);
162162 void printOffset(int64_t Offset);
163 void printTargetFlags(const MachineOperand &Op);
164163 void print(const MachineInstr &MI, unsigned OpIdx,
165164 const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
166165 LLT TypeToPrint, bool PrintDef = true);
777776 OS << " + " << Offset;
778777 }
779778
780 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
781 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
782 for (const auto &I : Flags) {
783 if (I.first == TF) {
784 return I.second;
785 }
786 }
787 return nullptr;
788 }
789
790 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
791 if (!Op.getTargetFlags())
792 return;
793 const auto *TII = Op.getParent()->getMF()->getSubtarget().getInstrInfo();
794 assert(TII && "expected instruction info");
795 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
796 OS << "target-flags(";
797 const bool HasDirectFlags = Flags.first;
798 const bool HasBitmaskFlags = Flags.second;
799 if (!HasDirectFlags && !HasBitmaskFlags) {
800 OS << ") ";
801 return;
802 }
803 if (HasDirectFlags) {
804 if (const auto *Name = getTargetFlagName(TII, Flags.first))
805 OS << Name;
806 else
807 OS << "";
808 }
809 if (!HasBitmaskFlags) {
810 OS << ") ";
811 return;
812 }
813 bool IsCommaNeeded = HasDirectFlags;
814 unsigned BitMask = Flags.second;
815 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
816 for (const auto &Mask : BitMasks) {
817 // Check if the flag's bitmask has the bits of the current mask set.
818 if ((BitMask & Mask.first) == Mask.first) {
819 if (IsCommaNeeded)
820 OS << ", ";
821 IsCommaNeeded = true;
822 OS << Mask.second;
823 // Clear the bits which were serialized from the flag's bitmask.
824 BitMask &= ~(Mask.first);
825 }
826 }
827 if (BitMask) {
828 // When the resulting flag's bitmask isn't zero, we know that we didn't
829 // serialize all of the bit flags.
830 if (IsCommaNeeded)
831 OS << ", ";
832 OS << "";
833 }
834 OS << ") ";
835 }
836
837779 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
838780 const TargetRegisterInfo *TRI,
839781 bool ShouldPrintRegisterTies, LLT TypeToPrint,
840782 bool PrintDef) {
841783 const MachineOperand &Op = MI.getOperand(OpIdx);
842 printTargetFlags(Op);
843784 switch (Op.getType()) {
844785 case MachineOperand::MO_Immediate:
845786 if (MI.isOperandSubregIdx(OpIdx)) {
787 MachineOperand::printTargetFlags(OS, Op);
846788 MachineOperand::printSubregIdx(OS, Op.getImm(), TRI);
847789 break;
848790 }
853795 case MachineOperand::MO_ConstantPoolIndex:
854796 case MachineOperand::MO_TargetIndex:
855797 case MachineOperand::MO_JumpTableIndex:
856 case MachineOperand::MO_ExternalSymbol: {
798 case MachineOperand::MO_ExternalSymbol:
799 case MachineOperand::MO_GlobalAddress: {
857800 unsigned TiedOperandIdx = 0;
858801 if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
859802 TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
867810 break;
868811 case MachineOperand::MO_FrameIndex:
869812 printStackObjectReference(Op.getIndex());
870 break;
871 case MachineOperand::MO_GlobalAddress:
872 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
873 printOffset(Op.getOffset());
874813 break;
875814 case MachineOperand::MO_BlockAddress:
876815 OS << "blockaddress(";
400400 return nullptr;
401401 }
402402
403 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
404 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
405 for (const auto &I : Flags) {
406 if (I.first == TF) {
407 return I.second;
408 }
409 }
410 return nullptr;
411 }
412
403413 void MachineOperand::printSubregIdx(raw_ostream &OS, uint64_t Index,
404414 const TargetRegisterInfo *TRI) {
405415 OS << "%subreg.";
409419 OS << Index;
410420 }
411421
422 void MachineOperand::printTargetFlags(raw_ostream &OS,
423 const MachineOperand &Op) {
424 if (!Op.getTargetFlags())
425 return;
426 const MachineFunction *MF = getMFIfAvailable(Op);
427 if (!MF)
428 return;
429
430 const auto *TII = MF->getSubtarget().getInstrInfo();
431 assert(TII && "expected instruction info");
432 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
433 OS << "target-flags(";
434 const bool HasDirectFlags = Flags.first;
435 const bool HasBitmaskFlags = Flags.second;
436 if (!HasDirectFlags && !HasBitmaskFlags) {
437 OS << ") ";
438 return;
439 }
440 if (HasDirectFlags) {
441 if (const auto *Name = getTargetFlagName(TII, Flags.first))
442 OS << Name;
443 else
444 OS << "";
445 }
446 if (!HasBitmaskFlags) {
447 OS << ") ";
448 return;
449 }
450 bool IsCommaNeeded = HasDirectFlags;
451 unsigned BitMask = Flags.second;
452 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
453 for (const auto &Mask : BitMasks) {
454 // Check if the flag's bitmask has the bits of the current mask set.
455 if ((BitMask & Mask.first) == Mask.first) {
456 if (IsCommaNeeded)
457 OS << ", ";
458 IsCommaNeeded = true;
459 OS << Mask.second;
460 // Clear the bits which were serialized from the flag's bitmask.
461 BitMask &= ~(Mask.first);
462 }
463 }
464 if (BitMask) {
465 // When the resulting flag's bitmask isn't zero, we know that we didn't
466 // serialize all of the bit flags.
467 if (IsCommaNeeded)
468 OS << ", ";
469 OS << "";
470 }
471 OS << ") ";
472 }
473
412474 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
413475 const TargetIntrinsicInfo *IntrinsicInfo) const {
414476 tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
424486 unsigned TiedOperandIdx,
425487 const TargetRegisterInfo *TRI,
426488 const TargetIntrinsicInfo *IntrinsicInfo) const {
489 printTargetFlags(OS, *this);
427490 switch (getType()) {
428491 case MachineOperand::MO_Register: {
429492 unsigned Reg = getReg();
527590 OS << printJumpTableEntryReference(getIndex());
528591 break;
529592 case MachineOperand::MO_GlobalAddress:
530 OS << "
531593 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
532 if (getOffset())
533 OS << "+" << getOffset();
534 OS << '>';
594 printOffset(OS, getOffset());
535595 break;
536596 case MachineOperand::MO_ExternalSymbol: {
537597 StringRef Name = getSymbolName();
607667 break;
608668 }
609669 }
610 if (unsigned TF = getTargetFlags())
611 OS << "[TF=" << TF << ']';
612670 }
613671
614672 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
28812881 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
28822882 return false;
28832883 if (!DefMI.getOperand(1).isImm())
2884 // Could be t2MOVi32imm
2884 // Could be t2MOVi32imm @xx
28852885 return false;
28862886
28872887 if (!MRI->hasOneNonDBGUse(Reg))
591591 return;
592592 }
593593 case PPC::LWZtoc: {
594 // Transform %r3 = LWZtoc , %r2
594 // Transform %r3 = LWZtoc @min1, %r2
595595 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
596596
597597 // Change the opcode to LWZ, and the global address operand to be a
635635 case PPC::LDtocCPT:
636636 case PPC::LDtocBA:
637637 case PPC::LDtoc: {
638 // Transform %x3 = LDtoc , %x2
638 // Transform %x3 = LDtoc @min1, %x2
639639 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
640640
641641 // Change the opcode to LD, and the global address operand to be a
666666 }
667667
668668 case PPC::ADDIStocHA: {
669 // Transform %xd = ADDIStocHA %x2,
669 // Transform %xd = ADDIStocHA %x2, @sym
670670 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
671671
672672 // Change the opcode to ADDIS8. If the global address is external, has
713713 return;
714714 }
715715 case PPC::LDtocL: {
716 // Transform %xd = LDtocL , %xs
716 // Transform %xd = LDtocL @sym, %xs
717717 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
718718
719719 // Change the opcode to LD. If the global address is external, has
756756 return;
757757 }
758758 case PPC::ADDItocL: {
759 // Transform %xd = ADDItocL %xs,
759 // Transform %xd = ADDItocL %xs, @sym
760760 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
761761
762762 // Change the opcode to ADDI8. If the global address is external, then
787787 return;
788788 }
789789 case PPC::ADDISgotTprelHA: {
790 // Transform: %xd = ADDISgotTprelHA %x2,
790 // Transform: %xd = ADDISgotTprelHA %x2, @sym
791791 // Into: %xd = ADDIS8 %x2, sym@got@tlsgd@ha
792792 assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
793793 const MachineOperand &MO = MI->getOperand(2);
804804 }
805805 case PPC::LDgotTprelL:
806806 case PPC::LDgotTprelL32: {
807 // Transform %xd = LDgotTprelL , %xs
807 // Transform %xd = LDgotTprelL @sym, %xs
808808 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
809809
810810 // Change the opcode to LD.
865865 return;
866866 }
867867 case PPC::ADDIStlsgdHA: {
868 // Transform: %xd = ADDIStlsgdHA %x2,
868 // Transform: %xd = ADDIStlsgdHA %x2, @sym
869869 // Into: %xd = ADDIS8 %x2, sym@got@tlsgd@ha
870870 assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
871871 const MachineOperand &MO = MI->getOperand(2);
881881 return;
882882 }
883883 case PPC::ADDItlsgdL:
884 // Transform: %xd = ADDItlsgdL %xs,
884 // Transform: %xd = ADDItlsgdL %xs, @sym
885885 // Into: %xd = ADDI8 %xs, sym@got@tlsgd@l
886886 case PPC::ADDItlsgdL32: {
887 // Transform: %rd = ADDItlsgdL32 %rs,
887 // Transform: %rd = ADDItlsgdL32 %rs, @sym
888888 // Into: %rd = ADDI %rs, sym@got@tlsgd
889889 const MachineOperand &MO = MI->getOperand(2);
890890 const GlobalValue *GValue = MO.getGlobal();
901901 return;
902902 }
903903 case PPC::GETtlsADDR:
904 // Transform: %x3 = GETtlsADDR %x3,
904 // Transform: %x3 = GETtlsADDR %x3, @sym
905905 // Into: BL8_NOP_TLS __tls_get_addr(sym at tlsgd)
906906 case PPC::GETtlsADDR32: {
907 // Transform: %r3 = GETtlsADDR32 %r3,
907 // Transform: %r3 = GETtlsADDR32 %r3, @sym
908908 // Into: BL_TLS __tls_get_addr(sym at tlsgd)@PLT
909909 EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSGD);
910910 return;
911911 }
912912 case PPC::ADDIStlsldHA: {
913 // Transform: %xd = ADDIStlsldHA %x2,
913 // Transform: %xd = ADDIStlsldHA %x2, @sym
914914 // Into: %xd = ADDIS8 %x2, sym@got@tlsld@ha
915915 assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
916916 const MachineOperand &MO = MI->getOperand(2);
926926 return;
927927 }
928928 case PPC::ADDItlsldL:
929 // Transform: %xd = ADDItlsldL %xs,
929 // Transform: %xd = ADDItlsldL %xs, @sym
930930 // Into: %xd = ADDI8 %xs, sym@got@tlsld@l
931931 case PPC::ADDItlsldL32: {
932 // Transform: %rd = ADDItlsldL32 %rs,
932 // Transform: %rd = ADDItlsldL32 %rs, @sym
933933 // Into: %rd = ADDI %rs, sym@got@tlsld
934934 const MachineOperand &MO = MI->getOperand(2);
935935 const GlobalValue *GValue = MO.getGlobal();
946946 return;
947947 }
948948 case PPC::GETtlsldADDR:
949 // Transform: %x3 = GETtlsldADDR %x3,
949 // Transform: %x3 = GETtlsldADDR %x3, @sym
950950 // Into: BL8_NOP_TLS __tls_get_addr(sym at tlsld)
951951 case PPC::GETtlsldADDR32: {
952 // Transform: %r3 = GETtlsldADDR32 %r3,
952 // Transform: %r3 = GETtlsldADDR32 %r3, @sym
953953 // Into: BL_TLS __tls_get_addr(sym at tlsld)@PLT
954954 EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSLD);
955955 return;
956956 }
957957 case PPC::ADDISdtprelHA:
958 // Transform: %xd = ADDISdtprelHA %xs,
958 // Transform: %xd = ADDISdtprelHA %xs, @sym
959959 // Into: %xd = ADDIS8 %xs, sym@dtprel@ha
960960 case PPC::ADDISdtprelHA32: {
961 // Transform: %rd = ADDISdtprelHA32 %rs,
961 // Transform: %rd = ADDISdtprelHA32 %rs, @sym
962962 // Into: %rd = ADDIS %rs, sym@dtprel@ha
963963 const MachineOperand &MO = MI->getOperand(2);
964964 const GlobalValue *GValue = MO.getGlobal();
975975 return;
976976 }
977977 case PPC::ADDIdtprelL:
978 // Transform: %xd = ADDIdtprelL %xs,
978 // Transform: %xd = ADDIdtprelL %xs, @sym
979979 // Into: %xd = ADDI8 %xs, sym@dtprel@l
980980 case PPC::ADDIdtprelL32: {
981 // Transform: %rd = ADDIdtprelL32 %rs,
981 // Transform: %rd = ADDIdtprelL32 %rs, @sym
982982 // Into: %rd = ADDI %rs, sym@dtprel@l
983983 const MachineOperand &MO = MI->getOperand(2);
984984 const GlobalValue *GValue = MO.getGlobal();
45174517
45184518 // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
45194519 // If it must be toc-referenced according to PPCSubTarget, we generate:
4520 // LDtocL(, ADDIStocHA(%x2, ))
4520 // LDtocL(@sym, ADDIStocHA(%x2, @sym))
45214521 // Otherwise we generate:
4522 // ADDItocL(ADDIStocHA(%x2, ), )
4522 // ADDItocL(ADDIStocHA(%x2, @sym), @sym)
45234523 SDValue GA = N->getOperand(0);
45244524 SDValue TOCbase = N->getOperand(1);
45254525 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
23152315 // For a method return value, we check the ZExt/SExt flags in attribute.
23162316 // We assume the following code sequence for method call.
23172317 // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
2318 // BL8_NOP ,...
2318 // BL8_NOP @func,...
23192319 // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
23202320 // %5 = COPY %x3; G8RC:%5
23212321 if (SrcReg == PPC::X3) {
2121 body: |
2222 bb.0:
2323 ; CHECK: Adding MCLOH_AdrpAdrp:
24 ; CHECK-NEXT: %x1 = ADRP
25 ; CHECK-NEXT: %x1 = ADRP
24 ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g3
25 ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g4
2626 ; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
27 ; CHECK-NEXT: %x1 = ADRP
28 ; CHECK-NEXT: %x1 = ADRP
27 ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g2
28 ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g3
2929 ; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
30 ; CHECK-NEXT: %x0 = ADRP
31 ; CHECK-NEXT: %x0 = ADRP
30 ; CHECK-NEXT: %x0 = ADRP target-flags(aarch64-page) @g0
31 ; CHECK-NEXT: %x0 = ADRP target-flags(aarch64-page) @g1
3232 %x0 = ADRP target-flags(aarch64-page) @g0
3333 %x0 = ADRP target-flags(aarch64-page) @g1
3434 %x1 = ADRP target-flags(aarch64-page) @g2
3737
3838 bb.1:
3939 ; CHECK-NEXT: Adding MCLOH_AdrpAdd:
40 ; CHECK-NEXT: %x20 = ADRP
41 ; CHECK-NEXT: %x3 = ADDXri %x20,
40 ; CHECK-NEXT: %x20 = ADRP target-flags(aarch64-page) @g0
41 ; CHECK-NEXT: %x3 = ADDXri %x20, target-flags(aarch64-pageoff) @g0
4242 ; CHECK-NEXT: Adding MCLOH_AdrpAdd:
43 ; CHECK-NEXT: %x1 = ADRP
44 ; CHECK-NEXT: %x1 = ADDXri %x1,
43 ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g0
44 ; CHECK-NEXT: %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g0
4545 %x1 = ADRP target-flags(aarch64-page) @g0
4646 %x9 = SUBXri undef %x11, 5, 0 ; should not affect MCLOH formation
4747 %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g0, 0
7272
7373 bb.5:
7474 ; CHECK-NEXT: Adding MCLOH_AdrpLdr:
75 ; CHECK-NEXT: %x5 = ADRP
76 ; CHECK-NEXT: %s6 = LDRSui %x5,
75 ; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page) @g2
76 ; CHECK-NEXT: %s6 = LDRSui %x5, target-flags(aarch64-pageoff) @g2
7777 ; CHECK-NEXT: Adding MCLOH_AdrpLdr:
78 ; CHECK-NEXT: %x4 = ADRP
79 ; CHECK-NEXT: %x4 = LDRXui %x4,
78 ; CHECK-NEXT: %x4 = ADRP target-flags(aarch64-page) @g2
79 ; CHECK-NEXT: %x4 = LDRXui %x4, target-flags(aarch64-pageoff) @g2
8080 %x4 = ADRP target-flags(aarch64-page) @g2
8181 %x4 = LDRXui %x4, target-flags(aarch64-pageoff) @g2
8282 %x5 = ADRP target-flags(aarch64-page) @g2
8484
8585 bb.6:
8686 ; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
87 ; CHECK-NEXT: %x5 = ADRP
88 ; CHECK-NEXT: %x6 = LDRXui %x5,
87 ; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2
88 ; CHECK-NEXT: %x6 = LDRXui %x5, target-flags(aarch64-pageoff, aarch64-got) @g2
8989 ; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
90 ; CHECK-NEXT: %x4 = ADRP
91 ; CHECK-NEXT: %x4 = LDRXui %x4,
90 ; CHECK-NEXT: %x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2
91 ; CHECK-NEXT: %x4 = LDRXui %x4, target-flags(aarch64-pageoff, aarch64-got) @g2
9292 %x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2
9393 %x4 = LDRXui %x4, target-flags(aarch64-pageoff, aarch64-got) @g2
9494 %x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2
103103
104104 bb.8:
105105 ; CHECK-NEXT: Adding MCLOH_AdrpAddLdr:
106 ; CHECK-NEXT: %x7 = ADRP [TF=1]
107 ; CHECK-NEXT: %x8 = ADDXri %x7,
106 ; CHECK-NEXT: %x7 = ADRP target-flags(aarch64-page) @g3
107 ; CHECK-NEXT: %x8 = ADDXri %x7, target-flags(aarch64-pageoff) @g3
108108 ; CHECK-NEXT: %d1 = LDRDui %x8, 8
109109 %x7 = ADRP target-flags(aarch64-page) @g3
110110 %x8 = ADDXri %x7, target-flags(aarch64-pageoff) @g3, 0
112112
113113 bb.9:
114114 ; CHECK-NEXT: Adding MCLOH_AdrpAdd:
115 ; CHECK-NEXT: %x3 = ADRP
116 ; CHECK-NEXT: %x3 = ADDXri %x3,
115 ; CHECK-NEXT: %x3 = ADRP target-flags(aarch64-page) @g3
116 ; CHECK-NEXT: %x3 = ADDXri %x3, target-flags(aarch64-pageoff) @g3
117117 ; CHECK-NEXT: Adding MCLOH_AdrpAdd:
118 ; CHECK-NEXT: %x5 = ADRP
119 ; CHECK-NEXT: %x2 = ADDXri %x5,
118 ; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page) @g3
119 ; CHECK-NEXT: %x2 = ADDXri %x5, target-flags(aarch64-pageoff) @g3
120120 ; CHECK-NEXT: Adding MCLOH_AdrpAddStr:
121 ; CHECK-NEXT: %x1 = ADRP
122 ; CHECK-NEXT: %x1 = ADDXri %x1,
121 ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g3
122 ; CHECK-NEXT: %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g3
123123 ; CHECK-NEXT: STRXui %xzr, %x1, 16
124124 %x1 = ADRP target-flags(aarch64-page) @g3
125125 %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g3, 0
137137
138138 bb.10:
139139 ; CHECK-NEXT: Adding MCLOH_AdrpLdr:
140 ; CHECK-NEXT: %x2 = ADRP
141 ; CHECK-NEXT: %x2 = LDRXui %x2,
140 ; CHECK-NEXT: %x2 = ADRP target-flags(aarch64-page) @g3
141 ; CHECK-NEXT: %x2 = LDRXui %x2, target-flags(aarch64-pageoff) @g3
142142 ; CHECK-NEXT: Adding MCLOH_AdrpLdrGotLdr:
143 ; CHECK-NEXT: %x1 = ADRP
144 ; CHECK-NEXT: %x1 = LDRXui %x1,
143 ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
144 ; CHECK-NEXT: %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
145145 ; CHECK-NEXT: %x1 = LDRXui %x1, 24
146146 %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
147147 %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
153153
154154 bb.11:
155155 ; CHECK-NEXT: Adding MCLOH_AdrpLdr
156 ; CHECK-NEXT: %x5 = ADRP
157 ; CHECK-NEXT: %x5 = LDRXui %x5,
156 ; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page) @g1
157 ; CHECK-NEXT: %x5 = LDRXui %x5, target-flags(aarch64-pageoff) @g1
158158 ; CHECK-NEXT: Adding MCLOH_AdrpLdrGotStr:
159 ; CHECK-NEXT: %x1 = ADRP
160 ; CHECK-NEXT: %x1 = LDRXui %x1,
159 ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
160 ; CHECK-NEXT: %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
161161 ; CHECK-NEXT: STRXui %xzr, %x1, 32
162162 %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
163163 %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
170170 bb.12:
171171 ; CHECK-NOT: MCLOH_AdrpAdrp
172172 ; CHECK: Adding MCLOH_AdrpAddLdr
173 ; %x9 = ADRP
174 ; %x9 = ADDXri %x9,
173 ; %x9 = ADRP @g4
174 ; %x9 = ADDXri %x9, @g4
175175 ; %x5 = LDRXui %x9, 0
176176 %x9 = ADRP target-flags(aarch64-page, aarch64-got) @g4
177177 %x9 = ADDXri %x9, target-flags(aarch64-pageoff, aarch64-got) @g4, 0
3636 }
3737 #
3838 # CHECK: ********** MI Scheduling **********
39 # CHECK: SU(2): %2:rgpr = t2MOVi32imm ; rGPR:%2
39 # CHECK: SU(2): %2:rgpr = t2MOVi32imm @g1; rGPR:%2
4040 # CHECK_A9: Latency : 2
4141 # CHECK_SWIFT: Latency : 2
4242 # CHECK_R52: Latency : 2
1212 ; DARWIN-IR: Successors according to CFG: %bb.[[SUCCESS:[0-9]+]]({{[0-9a-fx/= ]+}}100.00%) %bb.[[FAILURE:[0-9]+]]
1313 ; DARWIN-IR: %bb.[[SUCCESS]]:
1414 ; DARWIN-IR: %bb.[[FAILURE]]:
15 ; DARWIN-IR: CALL64pcrel32
15 ; DARWIN-IR: CALL64pcrel32 @__stack_chk_fail
1616
1717 ; MSVC-SELDAG: # Machine code for function test_branch_weights:
1818 ; MSVC-SELDAG: mem:Volatile LD4[@__security_cookie]
1919 ; MSVC-SELDAG: ST4[FixedStack0]
2020 ; MSVC-SELDAG: LD4[FixedStack0]
21 ; MSVC-SELDAG: CALLpcrel32
21 ; MSVC-SELDAG: CALLpcrel32 @__security_check_cookie
2222
2323 ; MSVC always uses selection DAG now.
2424 ; MSVC-IR: # Machine code for function test_branch_weights:
2525 ; MSVC-IR: mem:Volatile LD4[@__security_cookie]
2626 ; MSVC-IR: ST4[FixedStack0]
2727 ; MSVC-IR: LD4[FixedStack0]
28 ; MSVC-IR: CALLpcrel32
28 ; MSVC-IR: CALLpcrel32 @__security_check_cookie
2929
3030 define i32 @test_branch_weights(i32 %n) #0 {
3131 entry:
66 //
77 //===----------------------------------------------------------------------===//
88
9 #include "llvm/CodeGen/MachineOperand.h"
910 #include "llvm/ADT/ilist_node.h"
10 #include "llvm/CodeGen/MachineOperand.h"
1111 #include "llvm/IR/Constants.h"
1212 #include "llvm/IR/LLVMContext.h"
13 #include "llvm/IR/Module.h"
1314 #include "llvm/IR/ModuleSlotTracker.h"
1415 #include "llvm/Support/raw_ostream.h"
1516 #include "gtest/gtest.h"
234235 }
235236 }
236237
238 TEST(MachineOperandTest, PrintGlobalAddress) {
239 LLVMContext Ctx;
240 Module M("MachineOperandGVTest", Ctx);
241 M.getOrInsertGlobal("foo", Type::getInt32Ty(Ctx));
242
243 GlobalValue *GV = M.getNamedValue("foo");
244
245 // Create a MachineOperand with a global address and a positive offset and
246 // print it.
247 MachineOperand MO = MachineOperand::CreateGA(GV, 12);
248
249 // Checking some preconditions on the newly created
250 // MachineOperand.
251 ASSERT_TRUE(MO.isGlobal());
252 ASSERT_TRUE(MO.getGlobal() == GV);
253 ASSERT_TRUE(MO.getOffset() == 12);
254
255 std::string str;
256 // Print a MachineOperand containing a global address and a positive offset.
257 {
258 raw_string_ostream OS(str);
259 MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
260 ASSERT_TRUE(OS.str() == "@foo + 12");
261 }
262
263 str.clear();
264 MO.setOffset(-12);
265
266 // Print a MachineOperand containing a global address and a negative offset.
267 {
268 raw_string_ostream OS(str);
269 MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
270 ASSERT_TRUE(OS.str() == "@foo - 12");
271 }
272 }
273
237274 } // end namespace