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WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243763 91177308-0d34-0410-b5e6-96231b3b80d8 JF Bastien 5 years ago
8 changed file(s) with 292 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
3737 namespace {
3838
3939 class WebAssemblyAsmPrinter final : public AsmPrinter {
40 const WebAssemblyInstrInfo *TII;
41
4042 public:
4143 WebAssemblyAsmPrinter(TargetMachine &TM, std::unique_ptr Streamer)
42 : AsmPrinter(TM, std::move(Streamer)) {}
44 : AsmPrinter(TM, std::move(Streamer)), TII(nullptr) {}
4345
4446 private:
4547 const char *getPassName() const override {
5456 AsmPrinter::getAnalysisUsage(AU);
5557 }
5658
57 bool runOnMachineFunction(MachineFunction &F) override {
58 return AsmPrinter::runOnMachineFunction(F);
59 bool runOnMachineFunction(MachineFunction &MF) override {
60 TII = static_cast(
61 MF.getSubtarget().getInstrInfo());
62 return AsmPrinter::runOnMachineFunction(MF);
5963 }
6064
6165 //===------------------------------------------------------------------===//
7377 SmallString<128> Str;
7478 raw_svector_ostream OS(Str);
7579
80 unsigned NumDefs = MI->getDesc().getNumDefs();
81 assert(NumDefs <= 1 &&
82 "Instructions with multiple result values not implemented");
83
84 if (NumDefs != 0) {
85 const MachineOperand &MO = MI->getOperand(0);
86 unsigned Reg = MO.getReg();
87 OS << "(setlocal @" << TargetRegisterInfo::virtReg2Index(Reg) << ' ';
88 }
89
90 OS << '(';
91
92 bool PrintOperands = true;
7693 switch (MI->getOpcode()) {
94 case WebAssembly::ARGUMENT:
95 OS << "argument " << MI->getOperand(1).getImm();
96 PrintOperands = false;
97 break;
7798 default:
78 DEBUG(MI->print(dbgs()));
79 llvm_unreachable("Unhandled instruction");
99 OS << TII->getName(MI->getOpcode());
80100 break;
81101 }
102
103 if (PrintOperands)
104 for (const MachineOperand &MO : MI->uses()) {
105 if (MO.isReg() && MO.isImplicit())
106 continue;
107 unsigned Reg = MO.getReg();
108 OS << " @" << TargetRegisterInfo::virtReg2Index(Reg);
109 }
110 OS << ')';
111
112 if (NumDefs != 0)
113 OS << ')';
114
115 OS << '\n';
82116
83117 OutStreamer->EmitRawText(OS.str());
84118 }
140140 assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
141141 if (CallConv != CallingConv::C)
142142 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
143
144 // FIXME: Implement LowerReturn.
143 if (IsVarArg)
144 fail(DL, DAG, "WebAssembly doesn't support varargs yet");
145
146 SmallVector RetOps(1, Chain);
147 RetOps.append(OutVals.begin(), OutVals.end());
148 const SDValue Ops[] = {Chain, OutVals.front()};
149 Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, Ops);
145150
146151 return Chain;
147152 }
159164 if (MF.getFunction()->hasStructRetAttr())
160165 fail(DL, DAG, "WebAssembly doesn't support struct return yet");
161166
162 // FIXME: Implement LowerFormalArguments.
163 for (const ISD::InputArg &In : Ins)
164 InVals.push_back(DAG.getNode(ISD::UNDEF, DL, In.VT));
167 unsigned ArgNo = 0;
168 for (const ISD::InputArg &In : Ins) {
169 if (In.Flags.isZExt())
170 fail(DL, DAG, "WebAssembly hasn't implemented zext arguments");
171 if (In.Flags.isSExt())
172 fail(DL, DAG, "WebAssembly hasn't implemented sext arguments");
173 if (In.Flags.isInReg())
174 fail(DL, DAG, "WebAssembly hasn't implemented inreg arguments");
175 if (In.Flags.isSRet())
176 fail(DL, DAG, "WebAssembly hasn't implemented sret arguments");
177 if (In.Flags.isByVal())
178 fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
179 if (In.Flags.isInAlloca())
180 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
181 if (In.Flags.isNest())
182 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
183 if (In.Flags.isReturned())
184 fail(DL, DAG, "WebAssembly hasn't implemented returned arguments");
185 if (In.Flags.isInConsecutiveRegs())
186 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
187 if (In.Flags.isInConsecutiveRegsLast())
188 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
189 if (In.Flags.isSplit())
190 fail(DL, DAG, "WebAssembly hasn't implemented split arguments");
191 if (In.VT != MVT::i32)
192 fail(DL, DAG, "WebAssembly hasn't implemented non-i32 arguments");
193 if (!In.Used)
194 fail(DL, DAG, "WebAssembly hasn't implemented unused arguments");
195 // FIXME Do something with In.getOrigAlign()?
196 InVals.push_back(DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
197 DAG.getTargetConstant(ArgNo++, DL, MVT::i32)));
198 }
165199
166200 return Chain;
167201 }
2323
2424 enum {
2525 FIRST_NUMBER = ISD::BUILTIN_OP_END,
26 RETURN,
27 ARGUMENT,
2628
2729 // add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...
2830 };
0 //===- WebAssemblyInstrControl.td-WebAssembly control-flow ------*- tablegen -*-
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// \brief WebAssembly control-flow code-gen constructs.
11 ///
12 //===----------------------------------------------------------------------===//
13
14 /*
15 * TODO(jfb): Add the following.
16 *
17 * block: a fixed-length sequence of statements
18 * if: if statement
19 * do_while: do while statement, basically a loop with a conditional branch
20 * forever: infinite loop statement (like while (1)), basically an unconditional
21 * branch (back to the top of the loop)
22 * continue: continue to start of nested loop
23 * break: break to end from nested loop or block
24 * switch: switch statement with fallthrough
25 */
26
27 let hasSideEffects = 1, isReturn = 1, isTerminator = 1, hasCtrlDep = 1,
28 isBarrier = 1 in {
29 //FIXME return more than just int32.
30 def RETURN : I<(outs), (ins Int32:$val), [(WebAssemblyreturn Int32:$val)]>;
31 } // hasSideEffects = 1, isReturn = 1, isTerminator = 1, hasCtrlDep = 1,
32 // isBarrier = 1
2424 // WebAssembly-specific DAG Node Types.
2525 //===----------------------------------------------------------------------===//
2626
27 def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>;
28 def SDT_WebAssemblyReturn : SDTypeProfile<0, 1, []>;
29
2730 //===----------------------------------------------------------------------===//
2831 // WebAssembly-specific DAG Nodes.
2932 //===----------------------------------------------------------------------===//
33
34 def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT",
35 SDT_WebAssemblyArgument>;
36 def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN",
37 SDT_WebAssemblyReturn,
38 [SDNPHasChain, SDNPSideEffect]>;
3039
3140 //===----------------------------------------------------------------------===//
3241 // WebAssembly-specific Operands.
4554
4655 include "WebAssemblyInstrFormats.td"
4756
57 def ARGUMENT : I<(outs Int32:$res), (ins i32imm:$argno),
58 [(set Int32:$res, (WebAssemblyargument timm:$argno))]>;
59
4860 //===----------------------------------------------------------------------===//
4961 // Additional sets of instructions.
5062 //===----------------------------------------------------------------------===//
5163
5264 include "WebAssemblyInstrMemory.td"
5365 include "WebAssemblyInstrCall.td"
66 include "WebAssemblyInstrControl.td"
5467 include "WebAssemblyInstrInteger.td"
5568 include "WebAssemblyInstrFloat.td"
5669 include "WebAssemblyInstrConv.td"
165165
166166 void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {}
167167
168 void WebAssemblyPassConfig::addPostRegAlloc() {}
168 void WebAssemblyPassConfig::addPostRegAlloc() {
169 // FIXME: the following passes dislike virtual registers. Disable them for now
170 // so that basic tests can pass. Future patches will remedy this.
171 //
172 // Fails with: Regalloc must assign all vregs.
173 disablePass(&PrologEpilogCodeInserterID);
174 // Fails with: should be run after register allocation.
175 disablePass(&MachineCopyPropagationID);
176 }
169177
170178 void WebAssemblyPassConfig::addPreSched2() {}
171179
1111 ; CHECK-NOT: {{.*}} is not a recognized processor for this target
1212 ; INVALID: {{.*}} is not a recognized processor for this target
1313
14 define void @f(i64 %i_like_the_web) {
15 ret void
14 define i32 @f(i32 %i_like_the_web) {
15 ret i32 %i_like_the_web
1616 }
22 target datalayout = "e-p:32:32-i64:64-v128:8:128-n32:64-S128"
33 target triple = "wasm32-unknown-unknown"
44
5 declare i32 @llvm.ctlz.i32(i32, i1)
6 declare i32 @llvm.cttz.i32(i32, i1)
7 declare i32 @llvm.ctpop.i32(i32)
8
59 ; CHECK-LABEL: add32:
10 ; CHECK-NEXT: (setlocal @0 (argument 1))
11 ; CHECK-NEXT: (setlocal @1 (argument 0))
12 ; CHECK-NEXT: (setlocal @2 (ADD_I32 @1 @0))
13 ; CHECK-NEXT: (RETURN @2)
614 define i32 @add32(i32 %x, i32 %y) {
715 %a = add i32 %x, %y
816 ret i32 %a
917 }
18
19 ; CHECK-LABEL: sub32:
20 ; CHECK-NEXT: (setlocal @0 (argument 1))
21 ; CHECK-NEXT: (setlocal @1 (argument 0))
22 ; CHECK-NEXT: (setlocal @2 (SUB_I32 @1 @0))
23 ; CHECK-NEXT: (RETURN @2)
24 define i32 @sub32(i32 %x, i32 %y) {
25 %a = sub i32 %x, %y
26 ret i32 %a
27 }
28
29 ; CHECK-LABEL: mul32:
30 ; CHECK-NEXT: (setlocal @0 (argument 1))
31 ; CHECK-NEXT: (setlocal @1 (argument 0))
32 ; CHECK-NEXT: (setlocal @2 (MUL_I32 @1 @0))
33 ; CHECK-NEXT: (RETURN @2)
34 define i32 @mul32(i32 %x, i32 %y) {
35 %a = mul i32 %x, %y
36 ret i32 %a
37 }
38
39 ; CHECK-LABEL: sdiv32:
40 ; CHECK-NEXT: (setlocal @0 (argument 1))
41 ; CHECK-NEXT: (setlocal @1 (argument 0))
42 ; CHECK-NEXT: (setlocal @2 (SDIV_I32 @1 @0))
43 ; CHECK-NEXT: (RETURN @2)
44 define i32 @sdiv32(i32 %x, i32 %y) {
45 %a = sdiv i32 %x, %y
46 ret i32 %a
47 }
48
49 ; CHECK-LABEL: udiv32:
50 ; CHECK-NEXT: (setlocal @0 (argument 1))
51 ; CHECK-NEXT: (setlocal @1 (argument 0))
52 ; CHECK-NEXT: (setlocal @2 (UDIV_I32 @1 @0))
53 ; CHECK-NEXT: (RETURN @2)
54 define i32 @udiv32(i32 %x, i32 %y) {
55 %a = udiv i32 %x, %y
56 ret i32 %a
57 }
58
59 ; CHECK-LABEL: srem32:
60 ; CHECK-NEXT: (setlocal @0 (argument 1))
61 ; CHECK-NEXT: (setlocal @1 (argument 0))
62 ; CHECK-NEXT: (setlocal @2 (SREM_I32 @1 @0))
63 ; CHECK-NEXT: (RETURN @2)
64 define i32 @srem32(i32 %x, i32 %y) {
65 %a = srem i32 %x, %y
66 ret i32 %a
67 }
68
69 ; CHECK-LABEL: urem32:
70 ; CHECK-NEXT: (setlocal @0 (argument 1))
71 ; CHECK-NEXT: (setlocal @1 (argument 0))
72 ; CHECK-NEXT: (setlocal @2 (UREM_I32 @1 @0))
73 ; CHECK-NEXT: (RETURN @2)
74 define i32 @urem32(i32 %x, i32 %y) {
75 %a = urem i32 %x, %y
76 ret i32 %a
77 }
78
79 ; CHECK-LABEL: and32:
80 ; CHECK-NEXT: (setlocal @0 (argument 1))
81 ; CHECK-NEXT: (setlocal @1 (argument 0))
82 ; CHECK-NEXT: (setlocal @2 (AND_I32 @1 @0))
83 ; CHECK-NEXT: (RETURN @2)
84 define i32 @and32(i32 %x, i32 %y) {
85 %a = and i32 %x, %y
86 ret i32 %a
87 }
88
89 ; CHECK-LABEL: ior32:
90 ; CHECK-NEXT: (setlocal @0 (argument 1))
91 ; CHECK-NEXT: (setlocal @1 (argument 0))
92 ; CHECK-NEXT: (setlocal @2 (IOR_I32 @1 @0))
93 ; CHECK-NEXT: (RETURN @2)
94 define i32 @ior32(i32 %x, i32 %y) {
95 %a = or i32 %x, %y
96 ret i32 %a
97 }
98
99 ; CHECK-LABEL: xor32:
100 ; CHECK-NEXT: (setlocal @0 (argument 1))
101 ; CHECK-NEXT: (setlocal @1 (argument 0))
102 ; CHECK-NEXT: (setlocal @2 (XOR_I32 @1 @0))
103 ; CHECK-NEXT: (RETURN @2)
104 define i32 @xor32(i32 %x, i32 %y) {
105 %a = xor i32 %x, %y
106 ret i32 %a
107 }
108
109 ; CHECK-LABEL: shl32:
110 ; CHECK-NEXT: (setlocal @0 (argument 1))
111 ; CHECK-NEXT: (setlocal @1 (argument 0))
112 ; CHECK-NEXT: (setlocal @2 (SHL_I32 @1 @0))
113 ; CHECK-NEXT: (RETURN @2)
114 define i32 @shl32(i32 %x, i32 %y) {
115 %a = shl i32 %x, %y
116 ret i32 %a
117 }
118
119 ; CHECK-LABEL: shr32:
120 ; CHECK-NEXT: (setlocal @0 (argument 1))
121 ; CHECK-NEXT: (setlocal @1 (argument 0))
122 ; CHECK-NEXT: (setlocal @2 (SHR_I32 @1 @0))
123 ; CHECK-NEXT: (RETURN @2)
124 define i32 @shr32(i32 %x, i32 %y) {
125 %a = lshr i32 %x, %y
126 ret i32 %a
127 }
128
129 ; CHECK-LABEL: sar32:
130 ; CHECK-NEXT: (setlocal @0 (argument 1))
131 ; CHECK-NEXT: (setlocal @1 (argument 0))
132 ; CHECK-NEXT: (setlocal @2 (SAR_I32 @1 @0))
133 ; CHECK-NEXT: (RETURN @2)
134 define i32 @sar32(i32 %x, i32 %y) {
135 %a = ashr i32 %x, %y
136 ret i32 %a
137 }
138
139 ; CHECK-LABEL: clz32:
140 ; CHECK-NEXT: (setlocal @0 (argument 0))
141 ; CHECK-NEXT: (setlocal @1 (CLZ_I32 @0))
142 ; CHECK-NEXT: (RETURN @1)
143 define i32 @clz32(i32 %x) {
144 %a = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
145 ret i32 %a
146 }
147
148 ; CHECK-LABEL: ctz32:
149 ; CHECK-NEXT: (setlocal @0 (argument 0))
150 ; CHECK-NEXT: (setlocal @1 (CTZ_I32 @0))
151 ; CHECK-NEXT: (RETURN @1)
152 define i32 @ctz32(i32 %x) {
153 %a = call i32 @llvm.cttz.i32(i32 %x, i1 false)
154 ret i32 %a
155 }
156
157 ; CHECK-LABEL: popcnt32:
158 ; CHECK-NEXT: (setlocal @0 (argument 0))
159 ; CHECK-NEXT: (setlocal @1 (POPCNT_I32 @0))
160 ; CHECK-NEXT: (RETURN @1)
161 define i32 @popcnt32(i32 %x) {
162 %a = call i32 @llvm.ctpop.i32(i32 %x)
163 ret i32 %a
164 }