llvm.org GIT mirror llvm / 3ee2c33
R600/SI: Separate encoding and operand definitions into their own classes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213570 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 5 years ago
1 changed file(s) with 214 addition(s) and 172 deletion(s). Raw diff Collapse all Expand all
3636 let TSFlags{9} = SALU;
3737 }
3838
39 class Enc32 pattern> :
39 class Enc32 {
40
41 field bits<32> Inst;
42 int Size = 4;
43 }
44
45 class Enc64 {
46
47 field bits<64> Inst;
48 int Size = 8;
49 }
50
51 class VOP3Common pattern> :
4052 InstSI {
41
42 field bits<32> Inst;
43 let Size = 4;
44 }
45
46 class Enc64 pattern> :
47 InstSI {
48
49 field bits<64> Inst;
50 let Size = 8;
51 }
52
53 class VOP3Common pattern> :
54 Enc64 {
5553
5654 let mayLoad = 0;
5755 let mayStore = 0;
6462 // Scalar operations
6563 //===----------------------------------------------------------------------===//
6664
67 class SOP1 op, dag outs, dag ins, string asm, list pattern> :
68 Enc32 {
65 class SOP1e op> : Enc32 {
6966
7067 bits<7> SDST;
7168 bits<8> SSRC0;
7471 let Inst{15-8} = op;
7572 let Inst{22-16} = SDST;
7673 let Inst{31-23} = 0x17d; //encoding;
77
78 let mayLoad = 0;
79 let mayStore = 0;
80 let hasSideEffects = 0;
81 let SALU = 1;
82 }
83
84 class SOP2 op, dag outs, dag ins, string asm, list pattern> :
85 Enc32 {
86
74 }
75
76 class SOP2e op> : Enc32 {
77
8778 bits<7> SDST;
8879 bits<8> SSRC0;
8980 bits<8> SSRC1;
9384 let Inst{22-16} = SDST;
9485 let Inst{29-23} = op;
9586 let Inst{31-30} = 0x2; // encoding
96
97 let mayLoad = 0;
98 let mayStore = 0;
99 let hasSideEffects = 0;
100 let SALU = 1;
101 }
102
103 class SOPC op, dag outs, dag ins, string asm, list pattern> :
104 Enc32 {
87 }
88
89 class SOPCe op> : Enc32 {
10590
10691 bits<8> SSRC0;
10792 bits<8> SSRC1;
11095 let Inst{15-8} = SSRC1;
11196 let Inst{22-16} = op;
11297 let Inst{31-23} = 0x17e;
113
114 let DisableEncoding = "$dst";
115 let mayLoad = 0;
116 let mayStore = 0;
117 let hasSideEffects = 0;
118 let SALU = 1;
119 }
120
121 class SOPK op, dag outs, dag ins, string asm, list pattern> :
122 Enc32 {
98 }
99
100 class SOPKe op> : Enc32 {
123101
124102 bits <7> SDST;
125103 bits <16> SIMM16;
126
104
127105 let Inst{15-0} = SIMM16;
128106 let Inst{22-16} = SDST;
129107 let Inst{27-23} = op;
130108 let Inst{31-28} = 0xb; //encoding
131
132 let mayLoad = 0;
133 let mayStore = 0;
134 let hasSideEffects = 0;
135 let SALU = 1;
136 }
137
138 class SOPP op, dag ins, string asm, list pattern> : Enc32 <
139 (outs),
140 ins,
141 asm,
142 pattern > {
109 }
110
111 class SOPPe op> : Enc32 {
143112
144113 bits <16> simm16;
145114
146115 let Inst{15-0} = simm16;
147116 let Inst{22-16} = op;
148117 let Inst{31-23} = 0x17f; // encoding
149
150 let mayLoad = 0;
151 let mayStore = 0;
152 let hasSideEffects = 0;
153 let SALU = 1;
154 }
155
156 class SMRD op, bits<1> imm, dag outs, dag ins, string asm,
157 list pattern> : Enc32 {
118 }
119
120 class SMRDe op, bits<1> imm> : Enc32 {
158121
159122 bits<7> SDST;
160123 bits<7> SBASE;
161124 bits<8> OFFSET;
162
125
163126 let Inst{7-0} = OFFSET;
164127 let Inst{8} = imm;
165128 let Inst{14-9} = SBASE{6-1};
166129 let Inst{21-15} = SDST;
167130 let Inst{26-22} = op;
168131 let Inst{31-27} = 0x18; //encoding
132 }
133
134 class SOP1 op, dag outs, dag ins, string asm, list pattern> :
135 InstSI, SOP1e {
136
137 let mayLoad = 0;
138 let mayStore = 0;
139 let hasSideEffects = 0;
140 let SALU = 1;
141 }
142
143 class SOP2 op, dag outs, dag ins, string asm, list pattern> :
144 InstSI , SOP2e {
145
146 let mayLoad = 0;
147 let mayStore = 0;
148 let hasSideEffects = 0;
149 let SALU = 1;
150 }
151
152 class SOPC op, dag outs, dag ins, string asm, list pattern> :
153 InstSI, SOPCe {
154
155 let DisableEncoding = "$dst";
156 let mayLoad = 0;
157 let mayStore = 0;
158 let hasSideEffects = 0;
159 let SALU = 1;
160 }
161
162 class SOPK op, dag outs, dag ins, string asm, list pattern> :
163 InstSI , SOPKe {
164
165 let mayLoad = 0;
166 let mayStore = 0;
167 let hasSideEffects = 0;
168 let SALU = 1;
169 }
170
171 class SOPP op, dag ins, string asm, list pattern> :
172 InstSI <(outs), ins, asm, pattern >, SOPPe {
173
174 let mayLoad = 0;
175 let mayStore = 0;
176 let hasSideEffects = 0;
177 let SALU = 1;
178 }
179
180 class SMRD op, bits<1> imm, dag outs, dag ins, string asm,
181 list pattern> : InstSI, SMRDe {
169182
170183 let LGKM_CNT = 1;
171184 let SMRD = 1;
174187 //===----------------------------------------------------------------------===//
175188 // Vector ALU operations
176189 //===----------------------------------------------------------------------===//
177
178 let Uses = [EXEC] in {
179
180 class VOP1 op, dag outs, dag ins, string asm, list pattern> :
181 Enc32 {
190
191 class VOP1e op> : Enc32 {
182192
183193 bits<8> VDST;
184194 bits<9> SRC0;
185
195
186196 let Inst{8-0} = SRC0;
187197 let Inst{16-9} = op;
188198 let Inst{24-17} = VDST;
189199 let Inst{31-25} = 0x3f; //encoding
190
191 let mayLoad = 0;
192 let mayStore = 0;
193 let hasSideEffects = 0;
194 let UseNamedOperandTable = 1;
195 let VOP1 = 1;
196 }
197
198 class VOP2 op, dag outs, dag ins, string asm, list pattern> :
199 Enc32 {
200 }
201
202 class VOP2e op> : Enc32 {
200203
201204 bits<8> VDST;
202205 bits<9> SRC0;
203206 bits<8> VSRC1;
204
207
205208 let Inst{8-0} = SRC0;
206209 let Inst{16-9} = VSRC1;
207210 let Inst{24-17} = VDST;
208211 let Inst{30-25} = op;
209212 let Inst{31} = 0x0; //encoding
210
211 let mayLoad = 0;
212 let mayStore = 0;
213 let hasSideEffects = 0;
214 let UseNamedOperandTable = 1;
215 let VOP2 = 1;
216 }
217
218 class VOP3 op, dag outs, dag ins, string asm, list pattern> :
219 VOP3Common {
213 }
214
215 class VOP3e op> : Enc64 {
220216
221217 bits<8> dst;
222218 bits<2> src0_modifiers;
242238 let Inst{61} = src0_modifiers{0};
243239 let Inst{62} = src1_modifiers{0};
244240 let Inst{63} = src2_modifiers{0};
245
246 }
247
248 class VOP3b op, dag outs, dag ins, string asm, list pattern> :
249 VOP3Common {
241 }
242
243 class VOP3be op> : Enc64 {
250244
251245 bits<8> dst;
252246 bits<2> src0_modifiers;
269263 let Inst{61} = src0_modifiers{0};
270264 let Inst{62} = src1_modifiers{0};
271265 let Inst{63} = src2_modifiers{0};
272
273 }
274
275 class VOPC op, dag ins, string asm, list pattern> :
276 Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
266 }
267
268 class VOPCe op> : Enc32 {
277269
278270 bits<9> SRC0;
279271 bits<8> VSRC1;
282274 let Inst{16-9} = VSRC1;
283275 let Inst{24-17} = op;
284276 let Inst{31-25} = 0x3e;
285
286 let DisableEncoding = "$dst";
287 let mayLoad = 0;
288 let mayStore = 0;
289 let hasSideEffects = 0;
290 let UseNamedOperandTable = 1;
291 let VOPC = 1;
292 }
293
294 class VINTRP op, dag outs, dag ins, string asm, list pattern> :
295 Enc32 {
277 }
278
279 class VINTRPe op> : Enc32 {
296280
297281 bits<8> VDST;
298282 bits<8> VSRC;
305289 let Inst{17-16} = op;
306290 let Inst{25-18} = VDST;
307291 let Inst{31-26} = 0x32; // encoding
308
309 let neverHasSideEffects = 1;
310 let mayLoad = 1;
311 let mayStore = 0;
312 }
313
314 } // End Uses = [EXEC]
315
316 //===----------------------------------------------------------------------===//
317 // Vector I/O operations
318 //===----------------------------------------------------------------------===//
319
320 let Uses = [EXEC] in {
321
322 class DS op, dag outs, dag ins, string asm, list pattern> :
323 Enc64 {
292 }
293
294 class DSe op> : Enc64 {
324295
325296 bits<8> vdst;
326297 bits<1> gds;
339310 let Inst{47-40} = data0;
340311 let Inst{55-48} = data1;
341312 let Inst{63-56} = vdst;
342
343 let LGKM_CNT = 1;
344 }
345
346 class MUBUF op, dag outs, dag ins, string asm, list pattern> :
347 Enc64 {
313 }
314
315 class MUBUFe op> : Enc64 {
348316
349317 bits<12> offset;
350318 bits<1> offen;
373341 let Inst{54} = slc;
374342 let Inst{55} = tfe;
375343 let Inst{63-56} = soffset;
376
377 let VM_CNT = 1;
378 let EXP_CNT = 1;
379
380 let neverHasSideEffects = 1;
381 let UseNamedOperandTable = 1;
382 }
383
384 class MTBUF op, dag outs, dag ins, string asm, list pattern> :
385 Enc64 {
344 }
345
346 class MTBUFe op> : Enc64 {
386347
387348 bits<8> VDATA;
388349 bits<12> OFFSET;
413374 let Inst{54} = SLC;
414375 let Inst{55} = TFE;
415376 let Inst{63-56} = SOFFSET;
416
417 let VM_CNT = 1;
418 let EXP_CNT = 1;
419
420 let neverHasSideEffects = 1;
421 }
422
423 class MIMG op, dag outs, dag ins, string asm, list pattern> :
424 Enc64 {
377 }
378
379 class MIMGe op> : Enc64 {
425380
426381 bits<8> VDATA;
427382 bits<4> DMASK;
434389 bits<1> SLC;
435390 bits<8> VADDR;
436391 bits<7> SRSRC;
437 bits<7> SSAMP;
392 bits<7> SSAMP;
438393
439394 let Inst{11-8} = DMASK;
440395 let Inst{12} = UNORM;
450405 let Inst{47-40} = VDATA;
451406 let Inst{52-48} = SRSRC{6-2};
452407 let Inst{57-53} = SSAMP{6-2};
453
454 let VM_CNT = 1;
455 let EXP_CNT = 1;
456 let MIMG = 1;
457 }
458
459 def EXP : Enc64<
460 (outs),
461 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
462 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
463 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
464 [] > {
408 }
409
410 class EXPe : Enc64 {
465411
466412 bits<4> EN;
467413 bits<6> TGT;
483429 let Inst{47-40} = VSRC1;
484430 let Inst{55-48} = VSRC2;
485431 let Inst{63-56} = VSRC3;
486
432 }
433
434 let Uses = [EXEC] in {
435
436 class VOP1 op, dag outs, dag ins, string asm, list pattern> :
437 InstSI , VOP1e {
438
439 let mayLoad = 0;
440 let mayStore = 0;
441 let hasSideEffects = 0;
442 let UseNamedOperandTable = 1;
443 let VOP1 = 1;
444 }
445
446 class VOP2 op, dag outs, dag ins, string asm, list pattern> :
447 InstSI , VOP2e {
448
449 let mayLoad = 0;
450 let mayStore = 0;
451 let hasSideEffects = 0;
452 let UseNamedOperandTable = 1;
453 let VOP2 = 1;
454 }
455
456 class VOP3 op, dag outs, dag ins, string asm, list pattern> :
457 VOP3Common , VOP3e;
458
459 class VOP3b op, dag outs, dag ins, string asm, list pattern> :
460 VOP3Common , VOP3be;
461
462 class VOPC op, dag ins, string asm, list pattern> :
463 InstSI <(outs VCCReg:$dst), ins, asm, pattern>, VOPCe {
464
465 let DisableEncoding = "$dst";
466 let mayLoad = 0;
467 let mayStore = 0;
468 let hasSideEffects = 0;
469 let UseNamedOperandTable = 1;
470 let VOPC = 1;
471 }
472
473 class VINTRP op, dag outs, dag ins, string asm, list pattern> :
474 InstSI , VINTRPe {
475
476 let neverHasSideEffects = 1;
477 let mayLoad = 1;
478 let mayStore = 0;
479 }
480
481 } // End Uses = [EXEC]
482
483 //===----------------------------------------------------------------------===//
484 // Vector I/O operations
485 //===----------------------------------------------------------------------===//
486
487 let Uses = [EXEC] in {
488
489 class DS op, dag outs, dag ins, string asm, list pattern> :
490 InstSI , DSe {
491
492 let LGKM_CNT = 1;
493 }
494
495 class MUBUF op, dag outs, dag ins, string asm, list pattern> :
496 InstSI, MUBUFe {
497
498 let VM_CNT = 1;
487499 let EXP_CNT = 1;
500
501 let neverHasSideEffects = 1;
502 let UseNamedOperandTable = 1;
503 }
504
505 class MTBUF op, dag outs, dag ins, string asm, list pattern> :
506 InstSI, MTBUFe {
507
508 let VM_CNT = 1;
509 let EXP_CNT = 1;
510
511 let neverHasSideEffects = 1;
512 }
513
514 class MIMG op, dag outs, dag ins, string asm, list pattern> :
515 InstSI , MIMGe {
516
517 let VM_CNT = 1;
518 let EXP_CNT = 1;
519 let MIMG = 1;
520 }
521
522 def EXP : InstSI<
523 (outs),
524 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
525 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
526 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
527 [] >, EXPe {
528
529 let EXP_CNT = 1;
488530 }
489531
490532 } // End Uses = [EXEC]