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[LICM] Enable control flow hoisting by default Differential Revision: https://reviews.llvm.org/D54949 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347778 91177308-0d34-0410-b5e6-96231b3b80d8 John Brawn 9 months ago
3 changed file(s) with 14 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
9090 cl::desc("Disable memory promotion in LICM pass"));
9191
9292 static cl::opt ControlFlowHoisting(
93 "licm-control-flow-hoisting", cl::Hidden, cl::init(false),
93 "licm-control-flow-hoisting", cl::Hidden, cl::init(true),
9494 cl::desc("Enable control flow (and PHI) hoisting in LICM"));
9595
9696 static cl::opt MaxNumUsesTraversed(
None ; RUN: opt -S -licm < %s | FileCheck %s -check-prefixes=CHECK,CHECK-DISABLED
0 ; RUN: opt -S -licm < %s | FileCheck %s -check-prefixes=CHECK,CHECK-ENABLED
11 ; RUN: opt -S -licm -licm-control-flow-hoisting=1 < %s | FileCheck %s -check-prefixes=CHECK,CHECK-ENABLED
22 ; RUN: opt -S -licm -licm-control-flow-hoisting=0 < %s | FileCheck %s -check-prefixes=CHECK,CHECK-DISABLED
3 ; RUN: opt -passes='require,loop(licm)' -S < %s | FileCheck %s -check-prefixes=CHECK,CHECK-DISABLED
3 ; RUN: opt -passes='require,loop(licm)' -S < %s | FileCheck %s -check-prefixes=CHECK,CHECK-ENABLED
44 ; RUN: opt -passes='require,loop(licm)' -licm-control-flow-hoisting=1 -S < %s | FileCheck %s -check-prefixes=CHECK,CHECK-ENABLED
55 ; RUN: opt -passes='require,loop(licm)' -licm-control-flow-hoisting=0 -S < %s | FileCheck %s -check-prefixes=CHECK,CHECK-DISABLED
66
265265 ; variant/invariant values being stored to invariant address.
266266 ; test checks that the last element of the phi is extracted and scalar stored
267267 ; into the uniform address within the loop.
268 ; Since the condition and the phi is loop invariant, they are LICM'ed after
268 ; Since the condition and the phi is loop invariant, they are LICM'ed before
269269 ; vectorization.
270270 ; CHECK-LABEL: inv_val_store_to_inv_address_conditional_inv
271271 ; CHECK-NEXT: entry:
272 ; CHECK-NEXT: [[B1:%.*]] = bitcast i32* [[B:%.*]] to i8*
273 ; CHECK-NEXT: [[A4:%.*]] = bitcast i32* [[A:%.*]] to i8*
272274 ; CHECK-NEXT: [[NTRUNC:%.*]] = trunc i64 [[N:%.*]] to i32
273275 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[NTRUNC]], [[K:%.*]]
276 ; CHECK-NEXT: br i1 [[CMP]], label %[[COND_STORE_LICM:.*]], label %[[COND_STORE_K_LICM:.*]]
277 ; CHECK: [[COND_STORE_LICM]]:
278 ; CHECK-NEXT: br label %[[LATCH_LICM:.*]]
279 ; CHECK: [[COND_STORE_K_LICM]]:
280 ; CHECK-NEXT: br label %[[LATCH_LICM]]
281 ; CHECK: [[LATCH_LICM]]:
282 ; CHECK-NEXT: [[STOREVAL:%.*]] = phi i32 [ [[NTRUNC]], %[[COND_STORE_LICM]] ], [ [[K]], %[[COND_STORE_K_LICM]] ]
274283 ; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt i64 [[N]], 1
275284 ; CHECK-NEXT: [[SMAX:%.*]] = select i1 [[TMP0]], i64 [[N]], i64 1
276285 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[SMAX]], 4
277286 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]]
278287 ; CHECK: vector.memcheck:
279 ; CHECK-NEXT: [[A4:%.*]] = bitcast i32* [[A:%.*]] to i8*
280 ; CHECK-NEXT: [[B1:%.*]] = bitcast i32* [[B:%.*]] to i8*
281288 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[N]], 1
282289 ; CHECK-NEXT: [[SMAX2:%.*]] = select i1 [[TMP1]], i64 [[N]], i64 1
283290 ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[B]], i64 [[SMAX2]]
290297 ; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[SMAX]], 9223372036854775804
291298 ; CHECK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement <4 x i32> undef, i32 [[NTRUNC]], i32 0
292299 ; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT5]], <4 x i32> undef, <4 x i32> zeroinitializer
293 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i1> undef, i1 [[CMP]], i32 3
294 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> undef, i32 [[K]], i32 3
295 ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[BROADCAST_SPLAT6]], <4 x i32> [[TMP3]]
296 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[PREDPHI]], i32 3
297300 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
298301 ; CHECK: vector.body:
299302 ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
300303 ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[INDEX]]
301304 ; CHECK-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP6]] to <4 x i32>*
302305 ; CHECK-NEXT: store <4 x i32> [[BROADCAST_SPLAT6]], <4 x i32>* [[TMP7]], align 4
303 ; CHECK-NEXT: store i32 [[TMP5]], i32* [[A]], align 4
306 ; CHECK-NEXT: store i32 [[STOREVAL]], i32* [[A]], align 4
304307 ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
305308 ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
306309 ; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]]
320323 ; CHECK: cond_store_k:
321324 ; CHECK-NEXT: br label [[LATCH]]
322325 ; CHECK: latch:
323 ; CHECK-NEXT: [[STOREVAL:%.*]] = phi i32 [ [[NTRUNC]], [[COND_STORE]] ], [ [[K]], [[COND_STORE_K]] ]
324326 ; CHECK-NEXT: store i32 [[STOREVAL]], i32* [[A]], align 4
325327 ; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i64 [[I]], 1
326328 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i64 [[I_NEXT]], [[N]]