llvm.org GIT mirror llvm / 3ed0316
Add support for annotated disassembly output for X86 and arm. Per the October 12, 2012 Proposal for annotated disassembly output sent out by Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc tool now has a -mdis option to produced the marked up disassembly and a couple of small example test cases have been added. rdar://11764962 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166445 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Enderby 7 years ago
9 changed file(s) with 579 addition(s) and 142 deletion(s). Raw diff Collapse all Expand all
3232 /// The current set of available features.
3333 unsigned AvailableFeatures;
3434
35 /// True if we are printing marked up assembly.
36 bool UseMarkup;
37
3538 /// Utility function for printing annotations.
3639 void printAnnotation(raw_ostream &OS, StringRef Annot);
3740 public:
3841 MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii,
3942 const MCRegisterInfo &mri)
40 : CommentStream(0), MAI(mai), MII(mii), MRI(mri), AvailableFeatures(0) {}
43 : CommentStream(0), MAI(mai), MII(mii), MRI(mri), AvailableFeatures(0),
44 UseMarkup(0) {}
4145
4246 virtual ~MCInstPrinter();
4347
5862
5963 unsigned getAvailableFeatures() const { return AvailableFeatures; }
6064 void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; }
65
66 bool getUseMarkup() const { return UseMarkup; }
67 void setUseMarkup(bool Value) { UseMarkup = Value; }
6168 };
6269
6370 } // namespace llvm
145145 LLVMSymbolLookupCallback SymbolLookUp);
146146
147147 /**
148 * Set the disassembler's options. Returns 1 if it can set the Options and 0
149 * otherwise.
150 */
151 int LLVMSetDisasmOptions(LLVMDisasmContextRef DC, uint64_t Options);
152
153 /* The option to produce marked up assembly. */
154 #define LLVMDisassembler_Option_UseMarkup 1
155
156 /**
148157 * Dispose of a disassembler context.
149158 */
150159 void LLVMDisasmDispose(LLVMDisasmContextRef DC);
183183 }
184184 llvm_unreachable("Invalid DecodeStatus!");
185185 }
186
187 //
188 // LLVMSetDisasmOptions() sets the disassembler's options. It returns 1 if it
189 // can set all the Options and 0 otherwise.
190 //
191 int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options){
192 if (Options & LLVMDisassembler_Option_UseMarkup){
193 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
194 MCInstPrinter *IP = DC->getIP();
195 IP->setUseMarkup(1);
196 Options &= ~LLVMDisassembler_Option_UseMarkup;
197 }
198 return (Options == 0);
199 }
3838
3939 /// Prints the shift value with an immediate value.
4040 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
41 unsigned ShImm) {
41 unsigned ShImm, bool UseMarkup) {
4242 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
4343 return;
4444 O << ", ";
4646 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
4747 O << getShiftOpcStr(ShOpc);
4848
49 if (ShOpc != ARM_AM::rrx)
50 O << " #" << translateShiftImm(ShImm);
49 if (ShOpc != ARM_AM::rrx){
50 O << " ";
51 if (UseMarkup)
52 O << "
53 O << "#" << translateShiftImm(ShImm);
54 if (UseMarkup)
55 O << ">";
56 }
5157 }
5258
5359 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
6066 }
6167
6268 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
69 if (UseMarkup)
70 OS << "
6371 OS << getRegisterName(RegNo);
72 if (UseMarkup)
73 OS << ">";
6474 }
6575
6676 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
100110 printSBitModifierOperand(MI, 6, O);
101111 printPredicateOperand(MI, 4, O);
102112
103 O << '\t' << getRegisterName(Dst.getReg())
104 << ", " << getRegisterName(MO1.getReg());
105
106 O << ", " << getRegisterName(MO2.getReg());
113 O << '\t';
114 printRegName(O, Dst.getReg());
115 O << ", ";
116 printRegName(O, MO1.getReg());
117
118 O << ", ";
119 printRegName(O, MO2.getReg());
107120 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
108121 printAnnotation(O, Annot);
109122 return;
119132 printSBitModifierOperand(MI, 5, O);
120133 printPredicateOperand(MI, 3, O);
121134
122 O << '\t' << getRegisterName(Dst.getReg())
123 << ", " << getRegisterName(MO1.getReg());
135 O << '\t';
136 printRegName(O, Dst.getReg());
137 O << ", ";
138 printRegName(O, MO1.getReg());
124139
125140 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
126141 printAnnotation(O, Annot);
127142 return;
128143 }
129144
130 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
145 O << ", ";
146 if (UseMarkup)
147 O << "
148 O << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
149 if (UseMarkup)
150 O << ">";
131151 printAnnotation(O, Annot);
132152 return;
133153 }
151171 MI->getOperand(3).getImm() == -4) {
152172 O << '\t' << "push";
153173 printPredicateOperand(MI, 4, O);
154 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
174 O << "\t{";
175 printRegName(O, MI->getOperand(1).getReg());
176 O << "}";
155177 printAnnotation(O, Annot);
156178 return;
157179 }
174196 MI->getOperand(4).getImm() == 4) {
175197 O << '\t' << "pop";
176198 printPredicateOperand(MI, 5, O);
177 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
199 O << "\t{";
200 printRegName(O, MI->getOperand(0).getReg());
201 O << "}";
178202 printAnnotation(O, Annot);
179203 return;
180204 }
213237 O << "\tldm";
214238
215239 printPredicateOperand(MI, 1, O);
216 O << '\t' << getRegisterName(BaseReg);
240 O << '\t';
241 printRegName(O, BaseReg);
217242 if (Writeback) O << "!";
218243 O << ", ";
219244 printRegisterList(MI, 3, O);
239264 const MCOperand &Op = MI->getOperand(OpNo);
240265 if (Op.isReg()) {
241266 unsigned Reg = Op.getReg();
242 O << getRegisterName(Reg);
267 printRegName(O, Reg);
243268 } else if (Op.isImm()) {
269 if (UseMarkup)
270 O << "
244271 O << '#' << Op.getImm();
272 if (UseMarkup)
273 O << ">";
245274 } else {
246275 assert(Op.isExpr() && "unknown operand kind in printOperand");
247276 // If a symbolic branch target was added as a constant expression then print
264293 const MCOperand &MO1 = MI->getOperand(OpNum);
265294 if (MO1.isExpr())
266295 O << *MO1.getExpr();
267 else if (MO1.isImm())
268 O << "[pc, #" << MO1.getImm() << "]";
296 else if (MO1.isImm()) {
297 if (UseMarkup)
298 O << "
299 O << "[pc, ";
300 if (UseMarkup)
301 O << "
302 O << "#";
303 O << MO1.getImm();
304 if (UseMarkup)
305 O << ">";
306 O << "]";
307 if (UseMarkup)
308 O << ">";
309 }
269310 else
270311 llvm_unreachable("Unknown LDR label operand?");
271312 }
281322 const MCOperand &MO2 = MI->getOperand(OpNum+1);
282323 const MCOperand &MO3 = MI->getOperand(OpNum+2);
283324
284 O << getRegisterName(MO1.getReg());
325 printRegName(O, MO1.getReg());
285326
286327 // Print the shift opc.
287328 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
289330 if (ShOpc == ARM_AM::rrx)
290331 return;
291332
292 O << ' ' << getRegisterName(MO2.getReg());
333 O << ' ';
334 printRegName(O, MO2.getReg());
293335 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
294336 }
295337
298340 const MCOperand &MO1 = MI->getOperand(OpNum);
299341 const MCOperand &MO2 = MI->getOperand(OpNum+1);
300342
301 O << getRegisterName(MO1.getReg());
343 printRegName(O, MO1.getReg());
302344
303345 // Print the shift opc.
304346 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
305 ARM_AM::getSORegOffset(MO2.getImm()));
347 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
306348 }
307349
308350
316358 const MCOperand &MO2 = MI->getOperand(Op+1);
317359 const MCOperand &MO3 = MI->getOperand(Op+2);
318360
319 O << "[" << getRegisterName(MO1.getReg());
361 if (UseMarkup)
362 O << "
363 O << "[";
364 printRegName(O, MO1.getReg());
320365
321366 if (!MO2.getReg()) {
322 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
323 O << ", #"
324 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
325 << ARM_AM::getAM2Offset(MO3.getImm());
367 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
368 O << ", ";
369 if (UseMarkup)
370 O << "
371 O << "#";
372 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
373 O << ARM_AM::getAM2Offset(MO3.getImm());
374 if (UseMarkup)
375 O << ">";
376 }
326377 O << "]";
327 return;
328 }
329
330 O << ", "
331 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
332 << getRegisterName(MO2.getReg());
378 if (UseMarkup)
379 O << ">";
380 return;
381 }
382
383 O << ", ";
384 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
385 printRegName(O, MO2.getReg());
333386
334387 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
335 ARM_AM::getAM2Offset(MO3.getImm()));
388 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
336389 O << "]";
390 if (UseMarkup)
391 O << ">";
337392 }
338393
339394 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
340395 raw_ostream &O) {
341396 const MCOperand &MO1 = MI->getOperand(Op);
342397 const MCOperand &MO2 = MI->getOperand(Op+1);
343 O << "[" << getRegisterName(MO1.getReg()) << ", "
344 << getRegisterName(MO2.getReg()) << "]";
398 if (UseMarkup)
399 O << "
400 O << "[";
401 printRegName(O, MO1.getReg());
402 O << ", ";
403 printRegName(O, MO2.getReg());
404 O << "]";
405 if (UseMarkup)
406 O << ">";
345407 }
346408
347409 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
348410 raw_ostream &O) {
349411 const MCOperand &MO1 = MI->getOperand(Op);
350412 const MCOperand &MO2 = MI->getOperand(Op+1);
351 O << "[" << getRegisterName(MO1.getReg()) << ", "
352 << getRegisterName(MO2.getReg()) << ", lsl #1]";
413 if (UseMarkup)
414 O << "
415 O << "[";
416 printRegName(O, MO1.getReg());
417 O << ", ";
418 printRegName(O, MO2.getReg());
419 O << ", lsl ";
420 if (UseMarkup)
421 O << "
422 O << "#1";
423 if (UseMarkup)
424 O << ">";
425 O << "]";
426 if (UseMarkup)
427 O << ">";
353428 }
354429
355430 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
379454
380455 if (!MO1.getReg()) {
381456 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
457 if (UseMarkup)
458 O << "
382459 O << '#'
383460 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
384461 << ImmOffs;
385 return;
386 }
387
388 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
389 << getRegisterName(MO1.getReg());
462 if (UseMarkup)
463 O << ">";
464 return;
465 }
466
467 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
468 printRegName(O, MO1.getReg());
390469
391470 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
392 ARM_AM::getAM2Offset(MO2.getImm()));
471 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
393472 }
394473
395474 //===--------------------------------------------------------------------===//
402481 const MCOperand &MO2 = MI->getOperand(Op+1);
403482 const MCOperand &MO3 = MI->getOperand(Op+2);
404483
405 O << "[" << getRegisterName(MO1.getReg()) << "], ";
484 if (UseMarkup)
485 O << "
486 O << "[";
487 printRegName(O, MO1.getReg());
488 O << "], ";
489 if (UseMarkup)
490 O << ">";
406491
407492 if (MO2.getReg()) {
408 O << (char)ARM_AM::getAM3Op(MO3.getImm())
409 << getRegisterName(MO2.getReg());
493 O << (char)ARM_AM::getAM3Op(MO3.getImm());
494 printRegName(O, MO2.getReg());
410495 return;
411496 }
412497
413498 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
499 if (UseMarkup)
500 O << "
414501 O << '#'
415502 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
416503 << ImmOffs;
504 if (UseMarkup)
505 O << ">";
417506 }
418507
419508 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
422511 const MCOperand &MO2 = MI->getOperand(Op+1);
423512 const MCOperand &MO3 = MI->getOperand(Op+2);
424513
425 O << '[' << getRegisterName(MO1.getReg());
514 if (UseMarkup)
515 O << "
516 O << '[';
517 printRegName(O, MO1.getReg());
426518
427519 if (MO2.getReg()) {
428 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
429 << getRegisterName(MO2.getReg()) << ']';
520 O << ", ";
521 O << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
522 printRegName(O, MO2.getReg());
523 O << ']';
524 if (UseMarkup)
525 O << ">";
430526 return;
431527 }
432528
434530 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
435531 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
436532
437 if (ImmOffs || (op == ARM_AM::sub))
438 O << ", #"
533 if (ImmOffs || (op == ARM_AM::sub)) {
534 O << ", ";
535 if (UseMarkup)
536 O << "
537 O << "#"
439538 << ARM_AM::getAddrOpcStr(op)
440539 << ImmOffs;
540 if (UseMarkup)
541 O << ">";
542 }
441543 O << ']';
544 if (UseMarkup)
545 O << ">";
442546 }
443547
444548 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
466570 const MCOperand &MO2 = MI->getOperand(OpNum+1);
467571
468572 if (MO1.getReg()) {
469 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
470 << getRegisterName(MO1.getReg());
573 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
574 printRegName(O, MO1.getReg());
471575 return;
472576 }
473577
474578 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
579 if (UseMarkup)
580 O << "
475581 O << '#'
476582 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
477583 << ImmOffs;
584 if (UseMarkup)
585 O << ">";
478586 }
479587
480588 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
482590 raw_ostream &O) {
483591 const MCOperand &MO = MI->getOperand(OpNum);
484592 unsigned Imm = MO.getImm();
593 if (UseMarkup)
594 O << "
485595 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
596 if (UseMarkup)
597 O << ">";
486598 }
487599
488600 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
490602 const MCOperand &MO1 = MI->getOperand(OpNum);
491603 const MCOperand &MO2 = MI->getOperand(OpNum+1);
492604
493 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
605 O << (MO2.getImm() ? "" : "-");
606 printRegName(O, MO1.getReg());
494607 }
495608
496609 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
498611 raw_ostream &O) {
499612 const MCOperand &MO = MI->getOperand(OpNum);
500613 unsigned Imm = MO.getImm();
614 if (UseMarkup)
615 O << "
501616 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
617 if (UseMarkup)
618 O << ">";
502619 }
503620
504621
519636 return;
520637 }
521638
522 O << "[" << getRegisterName(MO1.getReg());
639 if (UseMarkup)
640 O << "
641 O << "[";
642 printRegName(O, MO1.getReg());
523643
524644 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
525645 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
526646 if (ImmOffs || Op == ARM_AM::sub) {
527 O << ", #"
647 O << ", ";
648 if (UseMarkup)
649 O << "
650 O << "#"
528651 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
529652 << ImmOffs * 4;
653 if (UseMarkup)
654 O << ">";
530655 }
531656 O << "]";
657 if (UseMarkup)
658 O << ">";
532659 }
533660
534661 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
536663 const MCOperand &MO1 = MI->getOperand(OpNum);
537664 const MCOperand &MO2 = MI->getOperand(OpNum+1);
538665
539 O << "[" << getRegisterName(MO1.getReg());
666 if (UseMarkup)
667 O << "
668 O << "[";
669 printRegName(O, MO1.getReg());
540670 if (MO2.getImm()) {
541671 // FIXME: Both darwin as and GNU as violate ARM docs here.
542672 O << ", :" << (MO2.getImm() << 3);
543673 }
544674 O << "]";
675 if (UseMarkup)
676 O << ">";
545677 }
546678
547679 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
548680 raw_ostream &O) {
549681 const MCOperand &MO1 = MI->getOperand(OpNum);
550 O << "[" << getRegisterName(MO1.getReg()) << "]";
682 if (UseMarkup)
683 O << "
684 O << "[";
685 printRegName(O, MO1.getReg());
686 O << "]";
687 if (UseMarkup)
688 O << ">";
551689 }
552690
553691 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
556694 const MCOperand &MO = MI->getOperand(OpNum);
557695 if (MO.getReg() == 0)
558696 O << "!";
559 else
560 O << ", " << getRegisterName(MO.getReg());
697 else {
698 O << ", ";
699 printRegName(O, MO.getReg());
700 }
561701 }
562702
563703 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
568708 int32_t lsb = CountTrailingZeros_32(v);
569709 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
570710 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
571 O << '#' << lsb << ", #" << width;
711 if (UseMarkup)
712 O << "
713 O << '#' << lsb;
714 if (UseMarkup)
715 O << ">";
716 O << ", ";
717 if (UseMarkup)
718 O << "
719 O << '#' << width;
720 if (UseMarkup)
721 O << ">";
572722 }
573723
574724 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
582732 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
583733 bool isASR = (ShiftOp & (1 << 5)) != 0;
584734 unsigned Amt = ShiftOp & 0x1f;
585 if (isASR)
586 O << ", asr #" << (Amt == 0 ? 32 : Amt);
587 else if (Amt)
588 O << ", lsl #" << Amt;
735 if (isASR) {
736 O << ", asr ";
737 if (UseMarkup)
738 O << "
739 O << "#" << (Amt == 0 ? 32 : Amt);
740 if (UseMarkup)
741 O << ">";
742 }
743 else if (Amt) {
744 O << ", lsl ";
745 if (UseMarkup)
746 O << "
747 O << "#" << Amt;
748 if (UseMarkup)
749 O << ">";
750 }
589751 }
590752
591753 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
594756 if (Imm == 0)
595757 return;
596758 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
597 O << ", lsl #" << Imm;
759 O << ", lsl ";
760 if (UseMarkup)
761 O << "
762 O << "#" << Imm;
763 if (UseMarkup)
764 O << ">";
598765 }
599766
600767 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
604771 if (Imm == 0)
605772 Imm = 32;
606773 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
607 O << ", asr #" << Imm;
774 O << ", asr ";
775 if (UseMarkup)
776 O << "
777 O << "#" << Imm;
778 if (UseMarkup)
779 O << ">";
608780 }
609781
610782 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
612784 O << "{";
613785 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
614786 if (i != OpNum) O << ", ";
615 O << getRegisterName(MI->getOperand(i).getReg());
787 printRegName(O, MI->getOperand(i).getReg());
616788 }
617789 O << "}";
618790 }
786958
787959 int32_t OffImm = (int32_t)MO.getImm();
788960
961 if (UseMarkup)
962 O << "
789963 if (OffImm == INT32_MIN)
790964 O << "#-0";
791965 else if (OffImm < 0)
792966 O << "#-" << -OffImm;
793967 else
794968 O << "#" << OffImm;
969 if (UseMarkup)
970 O << ">";
795971 }
796972
797973 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
798974 raw_ostream &O) {
975 if (UseMarkup)
976 O << "
799977 O << "#" << MI->getOperand(OpNum).getImm() * 4;
978 if (UseMarkup)
979 O << ">";
800980 }
801981
802982 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
803983 raw_ostream &O) {
804984 unsigned Imm = MI->getOperand(OpNum).getImm();
985 if (UseMarkup)
986 O << "
805987 O << "#" << (Imm == 0 ? 32 : Imm);
988 if (UseMarkup)
989 O << ">";
806990 }
807991
808992 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
8321016 return;
8331017 }
8341018
835 O << "[" << getRegisterName(MO1.getReg());
836 if (unsigned RegNum = MO2.getReg())
837 O << ", " << getRegisterName(RegNum);
1019 if (UseMarkup)
1020 O << "
1021 O << "[";
1022 printRegName(O, MO1.getReg());
1023 if (unsigned RegNum = MO2.getReg()) {
1024 O << ", ";
1025 printRegName(O, RegNum);
1026 }
8381027 O << "]";
1028 if (UseMarkup)
1029 O << ">";
8391030 }
8401031
8411032 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
8501041 return;
8511042 }
8521043
853 O << "[" << getRegisterName(MO1.getReg());
854 if (unsigned ImmOffs = MO2.getImm())
855 O << ", #" << ImmOffs * Scale;
1044 if (UseMarkup)
1045 O << "
1046 O << "[";
1047 printRegName(O, MO1.getReg());
1048 if (unsigned ImmOffs = MO2.getImm()) {
1049 O << ", ";
1050 if (UseMarkup)
1051 O << "
1052 O << "#" << ImmOffs * Scale;
1053 if (UseMarkup)
1054 O << ">";
1055 }
8561056 O << "]";
1057 if (UseMarkup)
1058 O << ">";
8571059 }
8581060
8591061 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
8891091 const MCOperand &MO2 = MI->getOperand(OpNum+1);
8901092
8911093 unsigned Reg = MO1.getReg();
892 O << getRegisterName(Reg);
1094 printRegName(O, Reg);
8931095
8941096 // Print the shift opc.
8951097 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
8961098 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
897 ARM_AM::getSORegOffset(MO2.getImm()));
1099 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
8981100 }
8991101
9001102 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
9071109 return;
9081110 }
9091111
910 O << "[" << getRegisterName(MO1.getReg());
1112 if (UseMarkup)
1113 O << "
1114 O << "[";
1115 printRegName(O, MO1.getReg());
9111116
9121117 int32_t OffImm = (int32_t)MO2.getImm();
9131118 bool isSub = OffImm < 0;
9141119 // Special value for #-0. All others are normal.
9151120 if (OffImm == INT32_MIN)
9161121 OffImm = 0;
917 if (isSub)
918 O << ", #-" << -OffImm;
919 else if (OffImm > 0)
920 O << ", #" << OffImm;
1122 if (isSub) {
1123 O << ", ";
1124 if (UseMarkup)
1125 O << "
1126 O << "#-" << -OffImm;
1127 if (UseMarkup)
1128 O << ">";
1129 }
1130 else if (OffImm > 0) {
1131 O << ", ";
1132 if (UseMarkup)
1133 O << "
1134 O << "#" << OffImm;
1135 if (UseMarkup)
1136 O << ">";
1137 }
9211138 O << "]";
1139 if (UseMarkup)
1140 O << ">";
9221141 }
9231142
9241143 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
9271146 const MCOperand &MO1 = MI->getOperand(OpNum);
9281147 const MCOperand &MO2 = MI->getOperand(OpNum+1);
9291148
930 O << "[" << getRegisterName(MO1.getReg());
1149 if (UseMarkup)
1150 O << "
1151 O << "[";
1152 printRegName(O, MO1.getReg());
9311153
9321154 int32_t OffImm = (int32_t)MO2.getImm();
9331155 // Don't print +0.
1156 if (OffImm != 0)
1157 O << ", ";
1158 if (OffImm != 0 && UseMarkup)
1159 O << "
9341160 if (OffImm == INT32_MIN)
935 O << ", #-0";
1161 O << "#-0";
9361162 else if (OffImm < 0)
937 O << ", #-" << -OffImm;
1163 O << "#-" << -OffImm;
9381164 else if (OffImm > 0)
939 O << ", #" << OffImm;
1165 O << "#" << OffImm;
1166 if (OffImm != 0 && UseMarkup)
1167 O << ">";
9401168 O << "]";
1169 if (UseMarkup)
1170 O << ">";
9411171 }
9421172
9431173 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
9511181 return;
9521182 }
9531183
954 O << "[" << getRegisterName(MO1.getReg());
1184 if (UseMarkup)
1185 O << "
1186 O << "[";
1187 printRegName(O, MO1.getReg());
9551188
9561189 int32_t OffImm = (int32_t)MO2.getImm();
9571190
9581191 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
9591192
9601193 // Don't print +0.
1194 if (OffImm != 0)
1195 O << ", ";
1196 if (OffImm != 0 && UseMarkup)
1197 O << "
9611198 if (OffImm == INT32_MIN)
962 O << ", #-0";
1199 O << "#-0";
9631200 else if (OffImm < 0)
964 O << ", #-" << -OffImm;
1201 O << "#-" << -OffImm;
9651202 else if (OffImm > 0)
966 O << ", #" << OffImm;
1203 O << "#" << OffImm;
1204 if (OffImm != 0 && UseMarkup)
1205 O << ">";
9671206 O << "]";
1207 if (UseMarkup)
1208 O << ">";
9681209 }
9691210
9701211 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
9731214 const MCOperand &MO1 = MI->getOperand(OpNum);
9741215 const MCOperand &MO2 = MI->getOperand(OpNum+1);
9751216
976 O << "[" << getRegisterName(MO1.getReg());
977 if (MO2.getImm())
978 O << ", #" << MO2.getImm() * 4;
1217 if (UseMarkup)
1218 O << "
1219 O << "[";
1220 printRegName(O, MO1.getReg());
1221 if (MO2.getImm()) {
1222 O << ", ";
1223 if (UseMarkup)
1224 O << "
1225 O << "#" << MO2.getImm() * 4;
1226 if (UseMarkup)
1227 O << ">";
1228 }
9791229 O << "]";
1230 if (UseMarkup)
1231 O << ">";
9801232 }
9811233
9821234 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
9841236 raw_ostream &O) {
9851237 const MCOperand &MO1 = MI->getOperand(OpNum);
9861238 int32_t OffImm = (int32_t)MO1.getImm();
987 // Don't print +0.
1239 O << ", ";
1240 if (UseMarkup)
1241 O << "
9881242 if (OffImm < 0)
989 O << ", #-" << -OffImm;
1243 O << "#-" << -OffImm;
9901244 else
991 O << ", #" << OffImm;
1245 O << "#" << OffImm;
1246 if (UseMarkup)
1247 O << ">";
9921248 }
9931249
9941250 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
10001256 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
10011257
10021258 // Don't print +0.
1259 if (OffImm != 0)
1260 O << ", ";
1261 if (OffImm != 0 && UseMarkup)
1262 O << "
10031263 if (OffImm == INT32_MIN)
1004 O << ", #-0";
1264 O << "#-0";
10051265 else if (OffImm < 0)
1006 O << ", #-" << -OffImm;
1266 O << "#-" << -OffImm;
10071267 else if (OffImm > 0)
1008 O << ", #" << OffImm;
1268 O << "#" << OffImm;
1269 if (OffImm != 0 && UseMarkup)
1270 O << ">";
10091271 }
10101272
10111273 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
10151277 const MCOperand &MO2 = MI->getOperand(OpNum+1);
10161278 const MCOperand &MO3 = MI->getOperand(OpNum+2);
10171279
1018 O << "[" << getRegisterName(MO1.getReg());
1280 if (UseMarkup)
1281 O << "
1282 O << "[";
1283 printRegName(O, MO1.getReg());
10191284
10201285 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1021 O << ", " << getRegisterName(MO2.getReg());
1286 O << ", ";
1287 printRegName(O, MO2.getReg());
10221288
10231289 unsigned ShAmt = MO3.getImm();
10241290 if (ShAmt) {
10251291 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1026 O << ", lsl #" << ShAmt;
1292 O << ", lsl ";
1293 if (UseMarkup)
1294 O << "
1295 O << "#" << ShAmt;
1296 if (UseMarkup)
1297 O << ">";
10271298 }
10281299 O << "]";
1300 if (UseMarkup)
1301 O << ">";
10291302 }
10301303
10311304 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
10321305 raw_ostream &O) {
10331306 const MCOperand &MO = MI->getOperand(OpNum);
1307 if (UseMarkup)
1308 O << "
10341309 O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
1310 if (UseMarkup)
1311 O << ">";
10351312 }
10361313
10371314 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
10391316 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
10401317 unsigned EltBits;
10411318 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1319 if (UseMarkup)
1320 O << "
10421321 O << "#0x";
10431322 O.write_hex(Val);
1323 if (UseMarkup)
1324 O << ">";
10441325 }
10451326
10461327 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
10471328 raw_ostream &O) {
10481329 unsigned Imm = MI->getOperand(OpNum).getImm();
1330 if (UseMarkup)
1331 O << "
10491332 O << "#" << Imm + 1;
1333 if (UseMarkup)
1334 O << ">";
10501335 }
10511336
10521337 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
10541339 unsigned Imm = MI->getOperand(OpNum).getImm();
10551340 if (Imm == 0)
10561341 return;
1057 O << ", ror #";
1342 O << ", ror ";
1343 if (UseMarkup)
1344 O << "
1345 O << "#";
10581346 switch (Imm) {
10591347 default: assert (0 && "illegal ror immediate!");
10601348 case 1: O << "8"; break;
10611349 case 2: O << "16"; break;
10621350 case 3: O << "24"; break;
10631351 }
1352 if (UseMarkup)
1353 O << ">";
10641354 }
10651355
10661356 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
10671357 raw_ostream &O) {
1358 if (UseMarkup)
1359 O << "
10681360 O << "#" << 16 - MI->getOperand(OpNum).getImm();
1361 if (UseMarkup)
1362 O << ">";
10691363 }
10701364
10711365 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
10721366 raw_ostream &O) {
1367 if (UseMarkup)
1368 O << "
10731369 O << "#" << 32 - MI->getOperand(OpNum).getImm();
1370 if (UseMarkup)
1371 O << ">";
10741372 }
10751373
10761374 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
10771375 raw_ostream &O) {
1376 if (UseMarkup)
1377 O << "
10781378 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1379 if (UseMarkup)
1380 O << ">";
10791381 }
10801382
10811383 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
10821384 raw_ostream &O) {
1083 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}";
1385 O << "{";
1386 printRegName(O, MI->getOperand(OpNum).getReg());
1387 O << "}";
10841388 }
10851389
10861390 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
10881392 unsigned Reg = MI->getOperand(OpNum).getReg();
10891393 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
10901394 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1091 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1395 O << "{";
1396 printRegName(O, Reg0);
1397 O << ", ";
1398 printRegName(O, Reg1);
1399 O << "}";
10921400 }
10931401
10941402 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
10971405 unsigned Reg = MI->getOperand(OpNum).getReg();
10981406 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
10991407 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1100 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1408 O << "{";
1409 printRegName(O, Reg0);
1410 O << ", ";
1411 printRegName(O, Reg1);
1412 O << "}";
11011413 }
11021414
11031415 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
11051417 // Normally, it's not safe to use register enum values directly with
11061418 // addition to get the next register, but for VFP registers, the
11071419 // sort order is guaranteed because they're all of the form D.
1108 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1109 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1110 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
1420 O << "{";
1421 printRegName(O, MI->getOperand(OpNum).getReg());
1422 O << ", ";
1423 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1424 O << ", ";
1425 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1426 O << "}";
11111427 }
11121428
11131429 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
11151431 // Normally, it's not safe to use register enum values directly with
11161432 // addition to get the next register, but for VFP registers, the
11171433 // sort order is guaranteed because they're all of the form D.
1118 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1119 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1120 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1121 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
1434 O << "{";
1435 printRegName(O, MI->getOperand(OpNum).getReg());
1436 O << ", ";
1437 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1438 O << ", ";
1439 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1440 O << ", ";
1441 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1442 O << "}";
11221443 }
11231444
11241445 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
11251446 unsigned OpNum,
11261447 raw_ostream &O) {
1127 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
1448 O << "{";
1449 printRegName(O, MI->getOperand(OpNum).getReg());
1450 O << "[]}";
11281451 }
11291452
11301453 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
11331456 unsigned Reg = MI->getOperand(OpNum).getReg();
11341457 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
11351458 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1136 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
1459 O << "{";
1460 printRegName(O, Reg0);
1461 O << "[], ";
1462 printRegName(O, Reg1);
1463 O << "[]}";
11371464 }
11381465
11391466 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
11421469 // Normally, it's not safe to use register enum values directly with
11431470 // addition to get the next register, but for VFP registers, the
11441471 // sort order is guaranteed because they're all of the form D.
1145 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1146 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
1147 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
1472 O << "{";
1473 printRegName(O, MI->getOperand(OpNum).getReg());
1474 O << "[], ";
1475 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1476 O << "[], ";
1477 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1478 O << "[]}";
11481479 }
11491480
11501481 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
11531484 // Normally, it's not safe to use register enum values directly with
11541485 // addition to get the next register, but for VFP registers, the
11551486 // sort order is guaranteed because they're all of the form D.
1156 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1157 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
1158 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1159 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "[]}";
1487 O << "{";
1488 printRegName(O, MI->getOperand(OpNum).getReg());
1489 O << "[], ";
1490 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1491 O << "[], ";
1492 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1493 O << "[], ";
1494 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1495 O << "[]}";
11601496 }
11611497
11621498 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
11651501 unsigned Reg = MI->getOperand(OpNum).getReg();
11661502 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
11671503 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1168 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
1504 O << "{";
1505 printRegName(O, Reg0);
1506 O << "[], ";
1507 printRegName(O, Reg1);
1508 O << "[]}";
11691509 }
11701510
11711511 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
11741514 // Normally, it's not safe to use register enum values directly with
11751515 // addition to get the next register, but for VFP registers, the
11761516 // sort order is guaranteed because they're all of the form D.
1177 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1178 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1179 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[]}";
1517 O << "{";
1518 printRegName(O, MI->getOperand(OpNum).getReg());
1519 O << "[], ";
1520 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1521 O << "[], ";
1522 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1523 O << "[]}";
11801524 }
11811525
11821526 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
11851529 // Normally, it's not safe to use register enum values directly with
11861530 // addition to get the next register, but for VFP registers, the
11871531 // sort order is guaranteed because they're all of the form D.
1188 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1189 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1190 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[], "
1191 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "[]}";
1532 O << "{";
1533 printRegName(O, MI->getOperand(OpNum).getReg());
1534 O << "[], ";
1535 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1536 O << "[], ";
1537 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1538 O << "[], ";
1539 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1540 O << "[]}";
11921541 }
11931542
11941543 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
11971546 // Normally, it's not safe to use register enum values directly with
11981547 // addition to get the next register, but for VFP registers, the
11991548 // sort order is guaranteed because they're all of the form D.
1200 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1201 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1202 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "}";
1549 O << "{";
1550 printRegName(O, MI->getOperand(OpNum).getReg());
1551 O << ", ";
1552 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1553 O << ", ";
1554 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1555 O << "}";
12031556 }
12041557
12051558 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
12081561 // Normally, it's not safe to use register enum values directly with
12091562 // addition to get the next register, but for VFP registers, the
12101563 // sort order is guaranteed because they're all of the form D.
1211 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1212 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1213 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << ", "
1214 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "}";
1215 }
1564 O << "{";
1565 printRegName(O, MI->getOperand(OpNum).getReg());
1566 O << ", ";
1567 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1568 O << ", ";
1569 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1570 O << ", ";
1571 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1572 O << "}";
1573 }
3333
3434 void X86ATTInstPrinter::printRegName(raw_ostream &OS,
3535 unsigned RegNo) const {
36 if (UseMarkup)
37 OS << "
3638 OS << '%' << getRegisterName(RegNo);
39 if (UseMarkup)
40 OS << ">";
3741 }
3842
3943 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
150154 raw_ostream &O) {
151155 const MCOperand &Op = MI->getOperand(OpNo);
152156 if (Op.isReg()) {
157 if (UseMarkup)
158 O << "
153159 O << '%' << getRegisterName(Op.getReg());
160 if (UseMarkup)
161 O << ">";
154162 } else if (Op.isImm()) {
163 if (UseMarkup)
164 O << "
155165 // Print X86 immediates as signed values.
156166 O << '$' << (int64_t)Op.getImm();
167 if (UseMarkup)
168 O << ">";
157169
158170 if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
159171 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
160172
161173 } else {
162174 assert(Op.isExpr() && "unknown operand kind in printOperand");
175 if (UseMarkup)
176 O << "
163177 O << '$' << *Op.getExpr();
178 if (UseMarkup)
179 O << ">";
164180 }
165181 }
166182
171187 const MCOperand &DispSpec = MI->getOperand(Op+3);
172188 const MCOperand &SegReg = MI->getOperand(Op+4);
173189
190 if (UseMarkup)
191 O << "
192
174193 // If this has a segment register, print it.
175194 if (SegReg.getReg()) {
176195 printOperand(MI, Op+4, O);
195214 O << ',';
196215 printOperand(MI, Op+2, O);
197216 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
198 if (ScaleVal != 1)
199 O << ',' << ScaleVal;
217 if (ScaleVal != 1) {
218 O << ',';
219 if (UseMarkup)
220 O << "
221 O << ScaleVal;
222 if (UseMarkup)
223 O << ">";
224 }
200225 }
201226 O << ')';
202227 }
203 }
228
229 if (UseMarkup)
230 O << ">";
231 }
0 # RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -mdis < %s | FileCheck %s
1 # CHECK: ldr ,
2 0x08 0x4c
3 # CHECK: push {, , }
4 0x86 0xb4
5 # CHECK: sub ,
6 0xa1 0xb0
0 # RUN: llvm-mc --mdis %s -triple=x86_64-apple-darwin9 2>&1 | FileCheck %s
1
2 # CHECK: movq :8>,
3 0x65 0x48 0x8b 0x0c 0x25 0x08 0x00 0x00 0x00
4 # CHECK: xorps ,
5 0x0f 0x57 0xd1
157157 AC_AsLex,
158158 AC_Assemble,
159159 AC_Disassemble,
160 AC_EDisassemble
160 AC_EDisassemble,
161 AC_MDisassemble
161162 };
162163
163164 static cl::opt
171172 "Disassemble strings of hex bytes"),
172173 clEnumValN(AC_EDisassemble, "edis",
173174 "Enhanced disassembly of strings of hex bytes"),
175 clEnumValN(AC_MDisassemble, "mdis",
176 "Marked up disassembly of strings of hex bytes"),
174177 clEnumValEnd));
175178
176179 static const Target *GetTarget(const char *ProgName) {
401404 OwningPtr
402405 STI(TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
403406
407 MCInstPrinter *IP;
404408 if (FileType == OFT_AssemblyFile) {
405 MCInstPrinter *IP =
409 IP =
406410 TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI, *MCII, *MRI, *STI);
407411 MCCodeEmitter *CE = 0;
408412 MCAsmBackend *MAB = 0;
435439 case AC_Assemble:
436440 Res = AssembleInput(ProgName, TheTarget, SrcMgr, Ctx, *Str, *MAI, *STI);
437441 break;
442 case AC_MDisassemble:
443 IP->setUseMarkup(1);
444 // Fall through to do disassembly.
438445 case AC_Disassemble:
439446 Res = Disassembler::disassemble(*TheTarget, TripleName, *STI, *Str,
440447 *Buffer, SrcMgr, Out->os());
2929 LLVMCreateDisasm
3030 LLVMDisasmDispose
3131 LLVMDisasmInstruction
32 LLVMSetDisasmOptions