llvm.org GIT mirror llvm / 3e55612
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 9 years ago
15 changed file(s) with 323 addition(s) and 70 deletion(s). Raw diff Collapse all Expand all
872872 case ARM::PICSTR: Opcode = ARM::STR; break;
873873 case ARM::PICSTRB: Opcode = ARM::STRB; break;
874874 case ARM::PICSTRH: Opcode = ARM::STRH; break;
875 case ARM::PICLDR: Opcode = ARM::LDR; break;
875 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
876876 case ARM::PICLDRB: Opcode = ARM::LDRB; break;
877877 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
878878 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
12191219 unsigned ScratchReg = MI->getOperand(1).getReg();
12201220 {
12211221 MCInst TmpInst;
1222 TmpInst.setOpcode(ARM::LDR);
1222 TmpInst.setOpcode(ARM::LDRi12);
12231223 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
12241224 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1225 TmpInst.addOperand(MCOperand::CreateReg(0));
12261225 TmpInst.addOperand(MCOperand::CreateImm(8));
12271226 // Predicate.
12281227 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
12311230 }
12321231 {
12331232 MCInst TmpInst;
1234 TmpInst.setOpcode(ARM::LDR);
1233 TmpInst.setOpcode(ARM::LDRi12);
12351234 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
12361235 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1237 TmpInst.addOperand(MCOperand::CreateReg(0));
12381236 TmpInst.addOperand(MCOperand::CreateImm(4));
12391237 // Predicate.
12401238 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
12431241 }
12441242 {
12451243 MCInst TmpInst;
1246 TmpInst.setOpcode(ARM::LDR);
1244 TmpInst.setOpcode(ARM::LDRi12);
12471245 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
12481246 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1249 TmpInst.addOperand(MCOperand::CreateReg(0));
12501247 TmpInst.addOperand(MCOperand::CreateImm(0));
12511248 // Predicate.
12521249 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
143143 if (isLoad)
144144 MemMI = BuildMI(MF, MI->getDebugLoc(),
145145 get(MemOpc), MI->getOperand(0).getReg())
146 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
146 .addReg(WBReg).addImm(0).addImm(Pred);
147147 else
148148 MemMI = BuildMI(MF, MI->getDebugLoc(),
149149 get(MemOpc)).addReg(MI->getOperand(1).getReg())
154154 if (isLoad)
155155 MemMI = BuildMI(MF, MI->getDebugLoc(),
156156 get(MemOpc), MI->getOperand(0).getReg())
157 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
157 .addReg(BaseReg).addImm(0).addImm(Pred);
158158 else
159159 MemMI = BuildMI(MF, MI->getDebugLoc(),
160160 get(MemOpc)).addReg(MI->getOperand(1).getReg())
822822
823823 switch (RC->getID()) {
824824 case ARM::GPRRegClassID:
825 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
826 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
825 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
826 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
827827 break;
828828 case ARM::SPRRegClassID:
829829 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
893893 int &FrameIndex) const {
894894 switch (MI->getOpcode()) {
895895 default: break;
896 case ARM::LDR:
896 case ARM::LDRrs:
897897 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
898898 if (MI->getOperand(1).isFI() &&
899899 MI->getOperand(2).isReg() &&
904904 return MI->getOperand(0).getReg();
905905 }
906906 break;
907 case ARM::LDRi12:
907908 case ARM::t2LDRi12:
908909 case ARM::tRestore:
909910 case ARM::VLDRD:
10771078 switch (Load1->getMachineOpcode()) {
10781079 default:
10791080 return false;
1080 case ARM::LDR:
1081 case ARM::LDRi12:
10811082 case ARM::LDRB:
10821083 case ARM::LDRD:
10831084 case ARM::LDRH:
10961097 switch (Load2->getMachineOpcode()) {
10971098 default:
10981099 return false;
1099 case ARM::LDR:
1100 case ARM::LDRi12:
11001101 case ARM::LDRB:
11011102 case ARM::LDRD:
11021103 case ARM::LDRH:
13611362 unsigned NumBits = 0;
13621363 unsigned Scale = 1;
13631364 switch (AddrMode) {
1365 case ARMII::AddrMode_i12: {
1366 ImmIdx = FrameRegIdx + 1;
1367 InstrOffs = MI.getOperand(ImmIdx).getImm();
1368 NumBits = 12;
1369 break;
1370 }
13641371 case ARMII::AddrMode2: {
13651372 ImmIdx = FrameRegIdx+2;
13661373 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
4949 AddrModeT2_so = 13,
5050 AddrModeT2_pc = 14, // +/- i12 for pc relative data
5151 AddrModeT2_i8s4 = 15, // i8 * 4
52 AddrMode_i12 = 16,
5253
5354 // Size* - Flags to keep track of the size of an instruction.
5455 SizeShift = 5,
12001200 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
12011201 .addReg(DestReg, getDefRegState(true), SubIdx)
12021202 .addConstantPoolIndex(Idx)
1203 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1203 .addImm(0).addImm(Pred).addReg(PredReg);
12041204 }
12051205
12061206 bool ARMBaseRegisterInfo::
13131313 switch (AddrMode) {
13141314 case ARMII::AddrModeT2_i8:
13151315 case ARMII::AddrModeT2_i12:
1316 case ARMII::AddrMode_i12:
13161317 InstrOffs = MI->getOperand(Idx+1).getImm();
13171318 Scale = 1;
13181319 break;
13741375 // return false for everything else.
13751376 unsigned Opc = MI->getOpcode();
13761377 switch (Opc) {
1377 case ARM::LDR: case ARM::LDRH: case ARM::LDRB:
1378 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRB:
13781379 case ARM::STR: case ARM::STRH: case ARM::STRB:
13791380 case ARM::t2LDRi12: case ARM::t2LDRi8:
13801381 case ARM::t2STRi12: case ARM::t2STRi8:
15181519 NumBits = 8;
15191520 Scale = 4;
15201521 break;
1522 case ARMII::AddrMode_i12:
15211523 case ARMII::AddrMode2:
15221524 NumBits = 12;
15231525 break;
18121814 const ARMBaseInstrInfo &TII,
18131815 const unsigned *CSRegs) {
18141816 return ((MI->getOpcode() == (int)ARM::VLDRD ||
1815 MI->getOpcode() == (int)ARM::LDR ||
1817 MI->getOpcode() == (int)ARM::LDRi12 ||
18161818 MI->getOpcode() == (int)ARM::t2LDRi12) &&
18171819 MI->getOperand(1).isFI() &&
18181820 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
18801882 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
18811883
18821884 // Move SP to SP upon entry to the function.
1883 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1885 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI);
18841886 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedAreaSize());
18851887 }
18861888
173173 const { return 0; }
174174 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
175175 unsigned Op) const { return 0; }
176 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
177 const { return 0; }
176178
177179 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
178180 /// machine operand requires relocation, record the relocation and return
602602 Scale = 4;
603603 break;
604604
605 case ARM::LDR:
605 case ARM::LDRi12:
606606 case ARM::LDRcp:
607607 case ARM::t2LDRpci:
608608 Bits = 12; // +-offset_12
448448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
449449 TII.get(ARM::LDRcp), DestReg)
450450 .addConstantPoolIndex(Idx)
451 .addReg(0).addImm(0));
451 .addImm(0));
452452
453453 return DestReg;
454454 }
749749 RC = ARM::GPRRegisterClass;
750750 break;
751751 case MVT::i32:
752 Opc = isThumb ? ARM::t2LDRi12 : ARM::LDR;
752 Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12;
753753 RC = ARM::GPRRegisterClass;
754754 break;
755755 case MVT::f32:
775775
776776 // The thumb and floating point instructions both take 2 operands, ARM takes
777777 // another register.
778 if (isFloat || isThumb)
779 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
780 TII.get(Opc), ResultReg)
781 .addReg(Base).addImm(Offset));
782 else
783 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
784 TII.get(Opc), ResultReg)
785 .addReg(Base).addReg(0).addImm(Offset));
778 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
779 TII.get(Opc), ResultReg)
780 .addReg(Base).addImm(Offset));
786781 return true;
787782 }
788783
7979
8080 bool SelectShifterOperandReg(SDValue N, SDValue &A,
8181 SDValue &B, SDValue &C);
82 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
83 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
84
8285 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
8386 SDValue &Offset, SDValue &Opc);
8487 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
9497 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
9598 SDValue &Opc) {
9699 SelectAddrMode2Worker(N, Base, Offset, Opc);
100 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
97101 // This always matches one way or another.
98102 return true;
99103 }
266270 MVT::i32);
267271 return true;
268272 }
273
274 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
275 SDValue &Base,
276 SDValue &OffImm) {
277 // Match simple R + imm12 operands.
278
279 // Base only.
280 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
281 if (N.getOpcode() == ISD::FrameIndex) {
282 // Match frame index...
283 int FI = cast(N)->getIndex();
284 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
285 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
286 return true;
287 } else if (N.getOpcode() == ARMISD::Wrapper &&
288 !(Subtarget->useMovt() &&
289 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
290 Base = N.getOperand(0);
291 } else
292 Base = N;
293 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
294 return true;
295 }
296
297 if (ConstantSDNode *RHS = dyn_cast(N.getOperand(1))) {
298 int RHSC = (int)RHS->getZExtValue();
299 if (N.getOpcode() == ISD::SUB)
300 RHSC = -RHSC;
301
302 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
303 Base = N.getOperand(0);
304 if (Base.getOpcode() == ISD::FrameIndex) {
305 int FI = cast(Base)->getIndex();
306 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
307 }
308 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
309 return true;
310 }
311 }
312
313 // Base only.
314 Base = N;
315 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
316 return true;
317 }
318
319
320
321 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
322 SDValue &Opc) {
323 if (N.getOpcode() == ISD::MUL) {
324 if (ConstantSDNode *RHS = dyn_cast(N.getOperand(1))) {
325 // X * [3,5,9] -> X + X * [2,4,8] etc.
326 int RHSC = (int)RHS->getZExtValue();
327 if (RHSC & 1) {
328 RHSC = RHSC & ~1;
329 ARM_AM::AddrOpc AddSub = ARM_AM::add;
330 if (RHSC < 0) {
331 AddSub = ARM_AM::sub;
332 RHSC = - RHSC;
333 }
334 if (isPowerOf2_32(RHSC)) {
335 unsigned ShAmt = Log2_32(RHSC);
336 Base = Offset = N.getOperand(0);
337 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
338 ARM_AM::lsl),
339 MVT::i32);
340 return true;
341 }
342 }
343 }
344 }
345
346 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB)
347 return false;
348
349 // Leave simple R +/- imm12 operands for LDRi12
350 if (N.getOpcode() == ISD::ADD) {
351 if (ConstantSDNode *RHS = dyn_cast(N.getOperand(1))) {
352 int RHSC = (int)RHS->getZExtValue();
353 if ((RHSC >= 0 && RHSC < 0x1000) ||
354 (RHSC < 0 && RHSC > -0x1000)) // 12 bits.
355 return false;
356 }
357 }
358
359 // Otherwise this is R +/- [possibly shifted] R.
360 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
361 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
362 unsigned ShAmt = 0;
363
364 Base = N.getOperand(0);
365 Offset = N.getOperand(1);
366
367 if (ShOpcVal != ARM_AM::no_shift) {
368 // Check to see if the RHS of the shift is a constant, if not, we can't fold
369 // it.
370 if (ConstantSDNode *Sh =
371 dyn_cast(N.getOperand(1).getOperand(1))) {
372 ShAmt = Sh->getZExtValue();
373 Offset = N.getOperand(1).getOperand(0);
374 } else {
375 ShOpcVal = ARM_AM::no_shift;
376 }
377 }
378
379 // Try matching (R shl C) + (R).
380 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
381 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
382 if (ShOpcVal != ARM_AM::no_shift) {
383 // Check to see if the RHS of the shift is a constant, if not, we can't
384 // fold it.
385 if (ConstantSDNode *Sh =
386 dyn_cast(N.getOperand(0).getOperand(1))) {
387 ShAmt = Sh->getZExtValue();
388 Offset = N.getOperand(0).getOperand(0);
389 Base = N.getOperand(1);
390 } else {
391 ShOpcVal = ARM_AM::no_shift;
392 }
393 }
394 }
395
396 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
397 MVT::i32);
398 return true;
399 }
400
401
402
403
404 //-----
269405
270406 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
271407 SDValue &Base,
17001836 } else {
17011837 SDValue Ops[] = {
17021838 CPIdx,
1703 CurDAG->getRegister(0, MVT::i32),
17041839 CurDAG->getTargetConstant(0, MVT::i32),
17051840 getAL(CurDAG),
17061841 CurDAG->getRegister(0, MVT::i32),
17071842 CurDAG->getEntryNode()
17081843 };
17091844 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1710 Ops, 6);
1845 Ops, 5);
17111846 }
17121847 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
17131848 return NULL;
103103 def AddrModeT2_so : AddrMode<13>;
104104 def AddrModeT2_pc : AddrMode<14>;
105105 def AddrModeT2_i8s4 : AddrMode<15>;
106 def AddrMode_i12 : AddrMode<16>;
106107
107108 // Instruction size.
108109 class SizeFlagVal val> {
398399 }
399400
400401 // loads
402
403 // LDR/LDRB
404 class AIldr1 op, bit opc22, dag oops, dag iops, AddrMode am, Format f,
405 InstrItinClass itin, string opc, string asm, list pattern>
406 : I
407 "", pattern> {
408 let Inst{27-25} = op;
409 let Inst{24} = 1; // 24 == P
410 // 23 == U
411 let Inst{22} = opc22;
412 let Inst{21} = 0; // 21 == W
413 let Inst{20} = 1;
414 }
415 // LDRH/LDRSB/LDRSH/LDRD
416 class AIldr2 op, bit opc22, bit opc20, dag oops, dag iops, AddrMode am,
417 Format f, InstrItinClass itin, string opc, string asm,
418 list pattern>
419 : I
420 "", pattern> {
421 let Inst{27-25} = 0b000;
422 let Inst{24} = 1; // 24 == P
423 // 23 == U
424 let Inst{22} = opc22;
425 let Inst{21} = 0; // 21 == W
426 let Inst{20} = opc20;
427
428 let Inst{7-4} = op;
429 }
430
431
432
433
401434 class AI2ldw
402435 string opc, string asm, list pattern>
403436 : I
3232 default: break;
3333 case ARM::LDR_PRE:
3434 case ARM::LDR_POST:
35 return ARM::LDR;
35 return ARM::LDRi12;
3636 case ARM::LDRH_PRE:
3737 case ARM::LDRH_POST:
3838 return ARM::LDRH;
381381
382382 // Define ARM specific addressing modes.
383383
384 // addrmode2base := reg +/- imm12
385 //
386 def addrmode2base : Operand,
387 ComplexPattern {
384
385 // addrmode_imm12 := reg +/- imm12
386 //
387 def addrmode_imm12 : Operand,
388 ComplexPattern {
389
390 string EncoderMethod = "getAddrModeImm12OpValue";
391 let PrintMethod = "printAddrModeImm12Operand";
392 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
393 }
394 // ldst_so_reg := reg +/- reg shop imm
395 //
396 def ldst_so_reg : Operand,
397 ComplexPattern {
398 // FIXME: Simplify the printer
388399 let PrintMethod = "printAddrMode2Operand";
389400 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
390401 }
391 // addrmode2shop := reg +/- reg shop imm
392 //
393 def addrmode2shop : Operand,
394 ComplexPattern {
395 let PrintMethod = "printAddrMode2Operand";
396 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
397 }
398
399 // addrmode2 := (addrmode2base || addrmode2shop)
402
403 // addrmode2 := reg +/- imm12
404 // := reg +/- reg shop imm
400405 //
401406 def addrmode2 : Operand,
402407 ComplexPattern {
796801 }
797802 }
798803
804 let canFoldAsLoad = 1, isReMaterializable = 1 in {
805 multiclass AI_ldr1
806 InstrItinClass iir, PatFrag opnode> {
807 // Note: We use the complex addrmode_imm12 rather than just an input
808 // GPR and a constrained immediate so that we can use this to match
809 // frame index references and avoid matching constant pool references.
810 def i12 : AIldr1<0b010, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
811 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
812 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
813 bits<4> Rt;
814 bits<17> addr;
815 let Inst{23} = addr{12}; // U (add = ('U' == 1))
816 let Inst{19-16} = addr{16-13}; // Rn
817 let Inst{15-12} = Rt;
818 let Inst{11-0} = addr{11-0}; // imm12
819 }
820 def rs : AIldr1<0b011, 0, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
821 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
822 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
823 bits<4> Rt;
824 bits<17> shift;
825 let Inst{23} = shift{12}; // U (add = ('U' == 1))
826 let Inst{19-16} = shift{16-13}; // Rn
827 let Inst{11-0} = shift{11-0};
828 }
829 }
830 }
831
799832 //===----------------------------------------------------------------------===//
800833 // Instructions
801834 //===----------------------------------------------------------------------===//
13641397 //
13651398
13661399 // Load
1367 let canFoldAsLoad = 1, isReMaterializable = 1 in
1368 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoad_r,
1369 "ldr", "\t$dst, $addr",
1370 [(set GPR:$dst, (load addrmode2:$addr))]>;
1400
1401
1402 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_i, IIC_iLoad_r,
1403 UnOpFrag<(load node:$Src)>>;
13711404
13721405 // Special LDR for loads from non-pc-relative constpools.
13731406 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
13741407 isReMaterializable = 1 in
1375 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoad_r,
1376 "ldr", "\t$dst, $addr", []>;
1408 def LDRcp : AIldr1<0b010, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1409 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", []> {
1410 bits<4> Rt;
1411 bits<17> addr;
1412 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1413 let Inst{19-16} = 0b1111;
1414 let Inst{15-12} = Rt;
1415 let Inst{11-0} = addr{11-0}; // imm12
1416 }
13771417
13781418 // Loads with zero extension
13791419 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
129129
130130 static int getLoadStoreMultipleOpcode(int Opcode) {
131131 switch (Opcode) {
132 case ARM::LDR:
132 case ARM::LDRi12:
133133 ++NumLDMGened;
134134 return ARM::LDM;
135135 case ARM::STR:
165165 }
166166
167167 static bool isi32Load(unsigned Opc) {
168 return Opc == ARM::LDR || isT2i32Load(Opc);
168 return Opc == ARM::LDRi12 || isT2i32Load(Opc);
169169 }
170170
171171 static bool isT2i32Store(unsigned Opc) {
439439 static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
440440 switch (MI->getOpcode()) {
441441 default: return 0;
442 case ARM::LDR:
442 case ARM::LDRi12:
443443 case ARM::STR:
444444 case ARM::t2LDRi8:
445445 case ARM::t2LDRi12:
577577
578578 static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) {
579579 switch (Opc) {
580 case ARM::LDR: return ARM::LDR_PRE;
580 case ARM::LDRi12: return ARM::LDR_PRE;
581581 case ARM::STR: return ARM::STR_PRE;
582582 case ARM::VLDRS: return ARM::VLDMS_UPD;
583583 case ARM::VLDRD: return ARM::VLDMD_UPD;
596596
597597 static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) {
598598 switch (Opc) {
599 case ARM::LDR: return ARM::LDR_POST;
599 case ARM::LDRi12: return ARM::LDR_POST;
600600 case ARM::STR: return ARM::STR_POST;
601601 case ARM::VLDRS: return ARM::VLDMS_UPD;
602602 case ARM::VLDRD: return ARM::VLDMD_UPD;
628628 DebugLoc dl = MI->getDebugLoc();
629629 bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||
630630 Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);
631 bool isAM2 = (Opcode == ARM::LDR || Opcode == ARM::STR);
632 if (isAM2 && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0)
633 return false;
634 if (isAM5 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0)
635 return false;
636 if (isT2i32Load(Opcode) || isT2i32Store(Opcode))
631 bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STR);
632 // FIXME: This special handling of LDRi12 is hackery until all of the ARM
633 // LDR/STR insns are moved away from the addrmode2 mega-instruction to
634 // the split (LDRi12/LDRrs) style instructions.
635 if (Opcode == ARM::LDRi12 || isT2i32Load(Opcode) || isT2i32Store(Opcode))
637636 if (MI->getOperand(2).getImm() != 0)
638637 return false;
638 if (isAM2 && Opcode != ARM::LDRi12
639 && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0)
640 return false;
641 if (isAM5 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0)
642 return false;
639643
640644 bool isLd = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD;
641645 // Can't do the merge if the destination register is the same as the would-be
781785 int Opcode = MI->getOpcode();
782786 switch (Opcode) {
783787 default: break;
784 case ARM::LDR:
785788 case ARM::STR:
786789 return MI->getOperand(1).isReg() && MI->getOperand(2).getReg() == 0;
787790 case ARM::VLDRS:
790793 case ARM::VLDRD:
791794 case ARM::VSTRD:
792795 return MI->getOperand(1).isReg();
796 case ARM::LDRi12:
793797 case ARM::t2LDRi8:
794798 case ARM::t2LDRi12:
795799 case ARM::t2STRi8:
817821
818822 static int getMemoryOpOffset(const MachineInstr *MI) {
819823 int Opcode = MI->getOpcode();
820 bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
824 bool isAM2 = Opcode == ARM::STR;
821825 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
822826 unsigned NumOperands = MI->getDesc().getNumOperands();
823827 unsigned OffField = MI->getOperand(NumOperands-3).getImm();
824828
825829 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
826830 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||
827 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8)
831 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||
832 Opcode == ARM::LDRi12)
828833 return OffField;
829834
830835 int Offset = isAM2
943948 assert((!isT2 || !OffReg) &&
944949 "Thumb2 ldrd / strd does not encode offset register!");
945950 unsigned NewOpc = (isLd)
946 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDR)
951 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
947952 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STR);
948953 DebugLoc dl = MBBI->getDebugLoc();
949954 // If this is a load and base register is killed, it may have been
13411346 // FIXME: VLDRS / VSTRS -> VLDRD / VSTRD
13421347 unsigned Scale = 1;
13431348 unsigned Opcode = Op0->getOpcode();
1344 if (Opcode == ARM::LDR)
1349 if (Opcode == ARM::LDRi12)
13451350 NewOpc = ARM::LDRD;
13461351 else if (Opcode == ARM::STR)
13471352 NewOpc = ARM::STRD;
13571362 return false;
13581363
13591364 // Make sure the offset registers match.
1360 if (!isT2 &&
1365 if (!isT2 && Opcode != ARM::LDRi12 &&
13611366 (Op0->getOperand(2).getReg() != Op1->getOperand(2).getReg()))
13621367 return false;
13631368
14041409 if (EvenReg == OddReg)
14051410 return false;
14061411 BaseReg = Op0->getOperand(1).getReg();
1407 if (!isT2)
1412 if (!isT2 && Opcode != ARM::LDRi12)
14081413 OffReg = Op0->getOperand(2).getReg();
14091414 Pred = llvm::getInstrPredicate(Op0, PredReg);
14101415 dl = Op0->getDebugLoc();
15121517 .addReg(EvenReg, RegState::Define)
15131518 .addReg(OddReg, RegState::Define)
15141519 .addReg(BaseReg);
1520 // For now, we're converting from LDRi12 to an insn that still
1521 // uses addrmode2, so we need an explicit offset reg. It should
1522 // always by reg0 since we're transforming LDRi12s. The old
1523 // was just being paranoid in allowing for anything else.
15151524 if (!isT2)
1516 MIB.addReg(OffReg);
1525 MIB.addReg(0);
15171526 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
15181527 ++NumLDRDFormed;
15191528 } else {
4747 /// getMachineOpValue - Return binary encoding of operand. If the machine
4848 /// operand requires relocation, record the relocation and return zero.
4949 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const;
50
51 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
52 /// operand.
53 unsigned getAddrModeImm12OpValue(const MCInst &MI, unsigned Op) const;
5054
5155 /// getCCOutOpValue - Return encoding of the 's' bit.
5256 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const {
168172 llvm_unreachable(0);
169173 }
170174 return 0;
175 }
176
177 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
178 /// operand.
179 unsigned ARMMCCodeEmitter::getAddrModeImm12OpValue(const MCInst &MI,
180 unsigned OpIdx) const {
181 // {17-13} = reg
182 // {12} = (U)nsigned (add == '1', sub == '0')
183 // {11-0} = imm12
184 const MCOperand &MO = MI.getOperand(OpIdx);
185 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
186 unsigned Reg = getARMRegisterNumbering(MO.getReg());
187 int32_t Imm12 = MO1.getImm();
188 uint32_t Binary;
189 Binary = Imm12 & 0xfff;
190 if (Imm12 >= 0)
191 Binary |= (1 << 12);
192 Binary |= (Reg << 13);
193 return Binary;
171194 }
172195
173196 unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI,
604604 const MCOperand &MO1 = MI->getOperand(OpNum);
605605 const MCOperand &MO2 = MI->getOperand(OpNum+1);
606606
607 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
608 printOperand(MI, OpNum, O);
609 return;
610 }
611
607612 O << "[" << getRegisterName(MO1.getReg());
608613
609614 unsigned OffImm = MO2.getImm();
591591 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I
592592 MISC("pred", "kOperandTypeARMPredicate"); // I, R
593593 MISC("it_pred", "kOperandTypeARMPredicate"); // I
594 MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I
595 MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I
594596 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
595597 MISC("am2offset", "kOperandTypeARMAddrMode2Offset"); // R, I
596598 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
806808 operandTypes.addEntry("kOperandTypeARMRotImm");
807809 operandTypes.addEntry("kOperandTypeARMSoImm2Part");
808810 operandTypes.addEntry("kOperandTypeARMPredicate");
811 operandTypes.addEntry("kOperandTypeAddrModeImm12");
812 operandTypes.addEntry("kOperandTypeLdStSOReg");
809813 operandTypes.addEntry("kOperandTypeARMAddrMode2");
810814 operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
811815 operandTypes.addEntry("kOperandTypeARMAddrMode3");