llvm.org GIT mirror llvm / 3e23463
Add MLA alias for ARMv4 support. Fix MLA defs to use register class GPRnopc. Add encoding tests for multiply instructions. (Alias for MUL/SMLAL/UMLAL added by r199026.) Patch by Zhaoshi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199491 91177308-0d34-0410-b5e6-96231b3b80d8 Renato Golin 6 years ago
3 changed file(s) with 54 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
36313631 Requires<[IsARM, NoV6, UseMulOps]>;
36323632 }
36333633
3634 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3634 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3635 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
36353636 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3636 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3637 Requires<[IsARM, HasV6, UseMulOps]> {
3637 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3638 Requires<[IsARM, HasV6, UseMulOps]> {
36383639 bits<4> Ra;
36393640 let Inst{15-12} = Ra;
36403641 }
36413642
36423643 let Constraints = "@earlyclobber $Rd" in
3643 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3644 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3645 4, IIC_iMAC32,
3646 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3647 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3648 Requires<[IsARM, NoV6]>;
3644 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3645 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3646 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3647 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3648 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3649 Requires<[IsARM, NoV6]>;
36493650
36503651 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
36513652 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
55825583 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
55835584 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
55845585 Requires<[IsARM, NoV6]>;
5586 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5587 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5588 pred:$p, cc_out:$s)>,
5589 Requires<[IsARM, NoV6]>;
55855590 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
55865591 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
55875592 Requires<[IsARM, NoV6]>;
3131
3232 @ Check that multiplication is supported
3333 mul r4, r5, r6
34 mla r4, r5, r6, r3
3435 smull r4, r5, r6, r3
3536 umull r4, r5, r6, r3
3637 smlal r4, r5, r6, r3
0 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
1
2 @ RUN: llvm-mc < %s -triple armv4-unknown-unknown -show-encoding | FileCheck %s --check-prefix=ARMV4
3
4 @ ARMV4: mul r0, r1, r2 @ encoding: [0x91,0x02,0x00,0xe0]
5 @ ARMV4: muls r0, r1, r2 @ encoding: [0x91,0x02,0x10,0xe0]
6 @ ARMV4: mulne r0, r1, r2 @ encoding: [0x91,0x02,0x00,0x10]
7 @ ARMV4: mulseq r0, r1, r2 @ encoding: [0x91,0x02,0x10,0x00]
8 mul r0, r1, r2
9 muls r0, r1, r2
10 mulne r0, r1, r2
11 mulseq r0, r1, r2
12
13 @ ARMV4: mla r0, r1, r2, r3 @ encoding: [0x91,0x32,0x20,0xe0]
14 @ ARMV4: mlas r0, r1, r2, r3 @ encoding: [0x91,0x32,0x30,0xe0]
15 @ ARMV4: mlane r0, r1, r2, r3 @ encoding: [0x91,0x32,0x20,0x10]
16 @ ARMV4: mlaseq r0, r1, r2, r3 @ encoding: [0x91,0x32,0x30,0x00]
17 mla r0, r1, r2, r3
18 mlas r0, r1, r2, r3
19 mlane r0, r1, r2, r3
20 mlaseq r0, r1, r2, r3
21
22 @ ARMV4: smlal r2, r3, r0, r1 @ encoding: [0x90,0x21,0xe3,0xe0]
23 @ ARMV4: smlals r2, r3, r0, r1 @ encoding: [0x90,0x21,0xf3,0xe0]
24 @ ARMV4: smlalne r2, r3, r0, r1 @ encoding: [0x90,0x21,0xe3,0x10]
25 @ ARMV4: smlalseq r2, r3, r0, r1 @ encoding: [0x90,0x21,0xf3,0x00]
26 smlal r2,r3,r0,r1
27 smlals r2,r3,r0,r1
28 smlalne r2,r3,r0,r1
29 smlalseq r2,r3,r0,r1
30
31 @ ARMV4: umlal r2, r3, r0, r1 @ encoding: [0x90,0x21,0xa3,0xe0]
32 @ ARMV4: umlals r2, r3, r0, r1 @ encoding: [0x90,0x21,0xb3,0xe0]
33 @ ARMV4: umlalne r2, r3, r0, r1 @ encoding: [0x90,0x21,0xa3,0x10]
34 @ ARMV4: umlalseq r2, r3, r0, r1 @ encoding: [0x90,0x21,0xb3,0x00]
35 umlal r2,r3,r0,r1
36 umlals r2,r3,r0,r1
37 umlalne r2,r3,r0,r1
38 umlalseq r2,r3,r0,r1