llvm.org GIT mirror llvm / 3e170f0
[WebAssembly] Add target feature for atomics Summary: This tracks the WebAssembly threads feature proposal at https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md Differential Revision: https://reviews.llvm.org/D37300 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312145 91177308-0d34-0410-b5e6-96231b3b80d8 Derek Schuff 3 years ago
10 changed file(s) with 50 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
127127 case WebAssembly::LOAD32_S_I64:
128128 case WebAssembly::LOAD32_U_I64:
129129 case WebAssembly::STORE32_I64:
130 case WebAssembly::ATOMIC_LOAD_I32:
130131 return 2;
131132 case WebAssembly::LOAD_I64:
132133 case WebAssembly::LOAD_F64:
2424
2525 def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true",
2626 "Enable 128-bit SIMD">;
27 def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
28 "Enable Atomics">;
2729
2830 //===----------------------------------------------------------------------===//
2931 // Architectures.
5456 def : ProcessorModel<"generic", NoSchedModel, []>;
5557
5658 // Latest and greatest experimental version of WebAssembly. Bugs included!
57 def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
59 def : ProcessorModel<"bleeding-edge", NoSchedModel,
60 [FeatureSIMD128, FeatureAtomics]>;
5861
5962 //===----------------------------------------------------------------------===//
6063 // Target Declaration
145145
146146 // Trap lowers to wasm unreachable
147147 setOperationAction(ISD::TRAP, MVT::Other, Legal);
148
149 setMaxAtomicSizeInBitsSupported(64);
148150 }
149151
150152 FastISel *WebAssemblyTargetLowering::createFastISel(
1111 ///
1212 //===----------------------------------------------------------------------===//
1313
14 // TODO: Implement atomic instructions.
15
16 //===----------------------------------------------------------------------===//
17 // Atomic fences
18 //===----------------------------------------------------------------------===//
19
20 // TODO: add atomic fences here...
21
2214 //===----------------------------------------------------------------------===//
2315 // Atomic loads
2416 //===----------------------------------------------------------------------===//
2517
26 // TODO: add atomic loads here...
18 let Defs = [ARGUMENTS] in {
19 // TODO: add the rest of the atomic loads
20 // TODO: factor out 0xfe atomic prefix?
21 def ATOMIC_LOAD_I32 : ATOMIC_I<(outs I32:$dst),
22 (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
23 [], "i32.atomic.load\t$dst, ${off}(${addr})${p2align}",
24 0xfe10>;
25 } // Defs = [ARGUMENTS]
26
27 // Select loads with no constant offset.
28 let Predicates = [HasAtomics] in {
29 def : Pat<(i32 (atomic_load I32:$addr)), (ATOMIC_LOAD_I32 0, 0, $addr)>;
30 }
2731
2832 //===----------------------------------------------------------------------===//
2933 // Atomic stores
4448 // Store-release-exclusives.
4549
4650 // And clear exclusive.
51
3030 class SIMD_I pattern,
3131 string asmstr = "", bits<32> inst = -1>
3232 : I, Requires<[HasSIMD128]>;
33
34 class ATOMIC_I pattern,
35 string asmstr = "", bits<32> inst = -1>
36 : I, Requires<[HasAtomics]>;
3337
3438 // Unary and binary instructions, for the local types that WebAssembly supports.
3539 multiclass UnaryInt i32Inst, bits<32> i64Inst> {
1919 def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
2020 def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
2121 AssemblerPredicate<"FeatureSIMD128", "simd128">;
22 def HasAtomics : Predicate<"Subtarget->hasAtomics()">,
23 AssemblerPredicate<"FeatureAtomics", "atomics">;
2224
2325 //===----------------------------------------------------------------------===//
2426 // WebAssembly-specific DAG Node Types.
9595 case WebAssembly::LOAD16_U_I64:
9696 case WebAssembly::LOAD32_S_I64:
9797 case WebAssembly::LOAD32_U_I64:
98 case WebAssembly::ATOMIC_LOAD_I32:
9899 RewriteP2Align(MI, WebAssembly::LoadP2AlignOperandNo);
99100 break;
100101 case WebAssembly::STORE_I32:
4040 const std::string &FS,
4141 const TargetMachine &TM)
4242 : WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD128(false),
43 CPUString(CPU), TargetTriple(TT), FrameLowering(),
43 HasAtomics(false), CPUString(CPU), TargetTriple(TT), FrameLowering(),
4444 InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
4545 TLInfo(TM, *this) {}
4646
2929
3030 class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
3131 bool HasSIMD128;
32 bool HasAtomics;
3233
3334 /// String name of used CPU.
3435 std::string CPUString;
7374 // Predicates used by WebAssemblyInstrInfo.td.
7475 bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
7576 bool hasSIMD128() const { return HasSIMD128; }
77 bool hasAtomics() const { return HasAtomics; }
7678
7779 /// Parses features string setting specified subtarget options. Definition of
7880 /// function is auto generated by tblgen.
0 ; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt
1 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -mattr=+atomics | FileCheck %s
2
3 ; Test that atomic loads are assembled properly.
4
5 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
6 target triple = "wasm32-unknown-unknown-wasm"
7
8 ; CHECK-LABEL: load_i32_atomic:
9 ; CHECK-NEXT: .param i32{{$}}
10 ; CHECK-NEXT: .result i32{{$}}
11 ; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
12 ; CHECK-NEXT: i32.atomic.load $push[[NUM:[0-9]+]]=, 0($pop[[L0]]){{$}}
13 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
14
15 define i32 @load_i32_atomic(i32 *%p) {
16 %v = load atomic i32, i32* %p seq_cst, align 4
17 ret i32 %v
18 }