llvm.org GIT mirror llvm / 3dbf247
Amending test/MC/ARM/thumb2-mclass.s to match its apparent original purpose (to test the ARMv6M/ARMv7M commonality), and creating a new test case for the differences between ARMv6M and ARMv7M git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198946 91177308-0d34-0410-b5e6-96231b3b80d8 Artyom Skrobov 6 years ago
2 changed file(s) with 47 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
0 @ RUN: llvm-mc -triple=thumbv7m-apple-darwin -show-encoding < %s | FileCheck %s
1 @ RUN: llvm-mc -triple=thumbv6m -show-encoding < %s | FileCheck %s
12 .syntax unified
23 .globl _func
34
45 @ Check that the assembler can handle the documented syntax from the ARM ARM.
5 @ These tests test instruction encodings specific to v7m & v7m (FeatureMClass).
6 @ These tests test instruction encodings specific to v6m & v7m (FeatureMClass).
67
78 @------------------------------------------------------------------------------
89 @ MRS
1819 mrs r0, msp
1920 mrs r0, psp
2021 mrs r0, primask
21 mrs r0, basepri
22 mrs r0, basepri_max
23 mrs r0, faultmask
2422 mrs r0, control
2523
2624 @ CHECK: mrs r0, apsr @ encoding: [0xef,0xf3,0x00,0x80]
3331 @ CHECK: mrs r0, msp @ encoding: [0xef,0xf3,0x08,0x80]
3432 @ CHECK: mrs r0, psp @ encoding: [0xef,0xf3,0x09,0x80]
3533 @ CHECK: mrs r0, primask @ encoding: [0xef,0xf3,0x10,0x80]
36 @ CHECK: mrs r0, basepri @ encoding: [0xef,0xf3,0x11,0x80]
37 @ CHECK: mrs r0, basepri_max @ encoding: [0xef,0xf3,0x12,0x80]
38 @ CHECK: mrs r0, faultmask @ encoding: [0xef,0xf3,0x13,0x80]
3934 @ CHECK: mrs r0, control @ encoding: [0xef,0xf3,0x14,0x80]
4035
4136 @------------------------------------------------------------------------------
6459 msr msp, r0
6560 msr psp, r0
6661 msr primask, r0
67 msr basepri, r0
68 msr basepri_max, r0
69 msr faultmask, r0
7062 msr control, r0
7163
7264 @ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88]
9183 @ CHECK: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x88]
9284 @ CHECK: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x88]
9385 @ CHECK: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x88]
94 @ CHECK: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x88]
95 @ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x88]
96 @ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x88]
9786 @ CHECK: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x88]
0 @ RUN: llvm-mc -triple=thumbv7m-apple-darwin -show-encoding < %s | FileCheck %s
1 @ RUN: not llvm-mc -triple=thumbv6 -show-encoding 2>&1 < %s | FileCheck %s --check-prefix=CHECK-V6M
2 .syntax unified
3 .globl _func
4
5 @ Check that the assembler can handle the documented syntax from the ARM ARM.
6 @ These tests test instruction encodings specific to ARMv7m.
7
8 @------------------------------------------------------------------------------
9 @ MRS
10 @------------------------------------------------------------------------------
11
12 mrs r0, basepri
13 mrs r0, basepri_max
14 mrs r0, faultmask
15
16 @ CHECK: mrs r0, basepri @ encoding: [0xef,0xf3,0x11,0x80]
17 @ CHECK: mrs r0, basepri_max @ encoding: [0xef,0xf3,0x12,0x80]
18 @ CHECK: mrs r0, faultmask @ encoding: [0xef,0xf3,0x13,0x80]
19
20 @------------------------------------------------------------------------------
21 @ MSR
22 @------------------------------------------------------------------------------
23
24 msr basepri, r0
25 msr basepri_max, r0
26 msr faultmask, r0
27
28 @ CHECK: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x88]
29 @ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x88]
30 @ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x88]
31
32 @ CHECK-V6M: error: invalid operand for instruction
33 @ CHECK-V6M-NEXT: mrs r0, basepri
34 @ CHECK-V6M: error: invalid operand for instruction
35 @ CHECK-V6M-NEXT: mrs r0, basepri_max
36 @ CHECK-V6M: error: invalid operand for instruction
37 @ CHECK-V6M-NEXT: mrs r0, faultmask
38 @ CHECK-V6M: error: invalid operand for instruction
39 @ CHECK-V6M-NEXT: msr basepri, r0
40 @ CHECK-V6M: error: invalid operand for instruction
41 @ CHECK-V6M-NEXT: msr basepri_max, r0
42 @ CHECK-V6M: error: invalid operand for instruction
43 @ CHECK-V6M-NEXT: msr faultmask, r0
44