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[X86][SSE] createVariablePermute - PSHUFB requires SSSE3 not just SSE3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327259 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 2 years ago
2 changed file(s) with 458 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
79987998 default:
79997999 break;
80008000 case MVT::v16i8:
8001 if (Subtarget.hasSSE3())
8001 if (Subtarget.hasSSSE3())
80028002 Opcode = X86ISD::PSHUFB;
80038003 break;
80048004 case MVT::v8i16:
80058005 if (Subtarget.hasVLX() && Subtarget.hasBWI())
80068006 Opcode = X86ISD::VPERMV;
8007 else if (Subtarget.hasSSE3()) {
8007 else if (Subtarget.hasSSSE3()) {
80088008 Opcode = X86ISD::PSHUFB;
80098009 ShuffleVT = MVT::v16i8;
80108010 }
80148014 if (Subtarget.hasAVX()) {
80158015 Opcode = X86ISD::VPERMILPV;
80168016 ShuffleVT = MVT::v4f32;
8017 } else if (Subtarget.hasSSE3()) {
8017 } else if (Subtarget.hasSSSE3()) {
80188018 Opcode = X86ISD::PSHUFB;
80198019 ShuffleVT = MVT::v16i8;
80208020 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefixes=SSE,SSE3
12 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSE,SSSE3
23 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
34 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop | FileCheck %s --check-prefixes=AVX,AVXNOVLBW,XOP
1011 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,+avx512vbmi | FileCheck %s --check-prefixes=AVX,AVX512VL,VLVBMI
1112
1213 define <2 x i64> @var_shuffle_v2i64(<2 x i64> %v, <2 x i64> %indices) nounwind {
14 ; SSE3-LABEL: var_shuffle_v2i64:
15 ; SSE3: # %bb.0:
16 ; SSE3-NEXT: movq %xmm1, %rax
17 ; SSE3-NEXT: andl $1, %eax
18 ; SSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
19 ; SSE3-NEXT: movq %xmm1, %rcx
20 ; SSE3-NEXT: andl $1, %ecx
21 ; SSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
22 ; SSE3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
23 ; SSE3-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
24 ; SSE3-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
25 ; SSE3-NEXT: retq
26 ;
1327 ; SSSE3-LABEL: var_shuffle_v2i64:
1428 ; SSSE3: # %bb.0:
1529 ; SSSE3-NEXT: movq %xmm1, %rax
5064 }
5165
5266 define <4 x i32> @var_shuffle_v4i32(<4 x i32> %v, <4 x i32> %indices) nounwind {
67 ; SSE3-LABEL: var_shuffle_v4i32:
68 ; SSE3: # %bb.0:
69 ; SSE3-NEXT: movd %xmm1, %eax
70 ; SSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,2,3]
71 ; SSE3-NEXT: movd %xmm2, %ecx
72 ; SSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
73 ; SSE3-NEXT: movd %xmm2, %edx
74 ; SSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,1,2,3]
75 ; SSE3-NEXT: movd %xmm1, %esi
76 ; SSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
77 ; SSE3-NEXT: andl $3, %eax
78 ; SSE3-NEXT: andl $3, %ecx
79 ; SSE3-NEXT: andl $3, %edx
80 ; SSE3-NEXT: andl $3, %esi
81 ; SSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
82 ; SSE3-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
83 ; SSE3-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
84 ; SSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
85 ; SSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
86 ; SSE3-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
87 ; SSE3-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
88 ; SSE3-NEXT: retq
89 ;
5390 ; SSSE3-LABEL: var_shuffle_v4i32:
5491 ; SSSE3: # %bb.0:
5592 ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [67372036,67372036,67372036,67372036]
90127 }
91128
92129 define <8 x i16> @var_shuffle_v8i16(<8 x i16> %v, <8 x i16> %indices) nounwind {
93 ; SSE-LABEL: var_shuffle_v8i16:
94 ; SSE: # %bb.0:
95 ; SSE-NEXT: pmullw {{.*}}(%rip), %xmm1
96 ; SSE-NEXT: paddw {{.*}}(%rip), %xmm1
97 ; SSE-NEXT: pshufb %xmm1, %xmm0
98 ; SSE-NEXT: retq
130 ; SSE3-LABEL: var_shuffle_v8i16:
131 ; SSE3: # %bb.0:
132 ; SSE3-NEXT: movd %xmm1, %r8d
133 ; SSE3-NEXT: pextrw $1, %xmm1, %r9d
134 ; SSE3-NEXT: pextrw $2, %xmm1, %r10d
135 ; SSE3-NEXT: pextrw $3, %xmm1, %esi
136 ; SSE3-NEXT: pextrw $4, %xmm1, %edi
137 ; SSE3-NEXT: pextrw $5, %xmm1, %eax
138 ; SSE3-NEXT: pextrw $6, %xmm1, %ecx
139 ; SSE3-NEXT: pextrw $7, %xmm1, %edx
140 ; SSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
141 ; SSE3-NEXT: andl $7, %r8d
142 ; SSE3-NEXT: andl $7, %r9d
143 ; SSE3-NEXT: andl $7, %r10d
144 ; SSE3-NEXT: andl $7, %esi
145 ; SSE3-NEXT: andl $7, %edi
146 ; SSE3-NEXT: andl $7, %eax
147 ; SSE3-NEXT: andl $7, %ecx
148 ; SSE3-NEXT: andl $7, %edx
149 ; SSE3-NEXT: movzwl -24(%rsp,%rdx,2), %edx
150 ; SSE3-NEXT: movd %edx, %xmm0
151 ; SSE3-NEXT: movzwl -24(%rsp,%rcx,2), %ecx
152 ; SSE3-NEXT: movd %ecx, %xmm1
153 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
154 ; SSE3-NEXT: movzwl -24(%rsp,%rax,2), %eax
155 ; SSE3-NEXT: movd %eax, %xmm0
156 ; SSE3-NEXT: movzwl -24(%rsp,%rdi,2), %eax
157 ; SSE3-NEXT: movd %eax, %xmm2
158 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
159 ; SSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
160 ; SSE3-NEXT: movzwl -24(%rsp,%rsi,2), %eax
161 ; SSE3-NEXT: movd %eax, %xmm0
162 ; SSE3-NEXT: movzwl -24(%rsp,%r10,2), %eax
163 ; SSE3-NEXT: movd %eax, %xmm1
164 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
165 ; SSE3-NEXT: movzwl -24(%rsp,%r9,2), %eax
166 ; SSE3-NEXT: movd %eax, %xmm3
167 ; SSE3-NEXT: movzwl -24(%rsp,%r8,2), %eax
168 ; SSE3-NEXT: movd %eax, %xmm0
169 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
170 ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
171 ; SSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
172 ; SSE3-NEXT: retq
173 ;
174 ; SSSE3-LABEL: var_shuffle_v8i16:
175 ; SSSE3: # %bb.0:
176 ; SSSE3-NEXT: pmullw {{.*}}(%rip), %xmm1
177 ; SSSE3-NEXT: paddw {{.*}}(%rip), %xmm1
178 ; SSSE3-NEXT: pshufb %xmm1, %xmm0
179 ; SSSE3-NEXT: retq
180 ;
181 ; SSE41-LABEL: var_shuffle_v8i16:
182 ; SSE41: # %bb.0:
183 ; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm1
184 ; SSE41-NEXT: paddw {{.*}}(%rip), %xmm1
185 ; SSE41-NEXT: pshufb %xmm1, %xmm0
186 ; SSE41-NEXT: retq
99187 ;
100188 ; AVXNOVLBW-LABEL: var_shuffle_v8i16:
101189 ; AVXNOVLBW: # %bb.0:
136224 }
137225
138226 define <16 x i8> @var_shuffle_v16i8(<16 x i8> %v, <16 x i8> %indices) nounwind {
139 ; SSE-LABEL: var_shuffle_v16i8:
140 ; SSE: # %bb.0:
141 ; SSE-NEXT: pshufb %xmm1, %xmm0
142 ; SSE-NEXT: retq
227 ; SSE3-LABEL: var_shuffle_v16i8:
228 ; SSE3: # %bb.0:
229 ; SSE3-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
230 ; SSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
231 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
232 ; SSE3-NEXT: andl $15, %eax
233 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
234 ; SSE3-NEXT: movd %eax, %xmm8
235 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
236 ; SSE3-NEXT: andl $15, %eax
237 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
238 ; SSE3-NEXT: movd %eax, %xmm15
239 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
240 ; SSE3-NEXT: andl $15, %eax
241 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
242 ; SSE3-NEXT: movd %eax, %xmm9
243 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
244 ; SSE3-NEXT: andl $15, %eax
245 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
246 ; SSE3-NEXT: movd %eax, %xmm3
247 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
248 ; SSE3-NEXT: andl $15, %eax
249 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
250 ; SSE3-NEXT: movd %eax, %xmm10
251 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
252 ; SSE3-NEXT: andl $15, %eax
253 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
254 ; SSE3-NEXT: movd %eax, %xmm7
255 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
256 ; SSE3-NEXT: andl $15, %eax
257 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
258 ; SSE3-NEXT: movd %eax, %xmm11
259 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
260 ; SSE3-NEXT: andl $15, %eax
261 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
262 ; SSE3-NEXT: movd %eax, %xmm6
263 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
264 ; SSE3-NEXT: andl $15, %eax
265 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
266 ; SSE3-NEXT: movd %eax, %xmm12
267 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
268 ; SSE3-NEXT: andl $15, %eax
269 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
270 ; SSE3-NEXT: movd %eax, %xmm5
271 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
272 ; SSE3-NEXT: andl $15, %eax
273 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
274 ; SSE3-NEXT: movd %eax, %xmm13
275 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
276 ; SSE3-NEXT: andl $15, %eax
277 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
278 ; SSE3-NEXT: movd %eax, %xmm4
279 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
280 ; SSE3-NEXT: andl $15, %eax
281 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
282 ; SSE3-NEXT: movd %eax, %xmm14
283 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
284 ; SSE3-NEXT: andl $15, %eax
285 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
286 ; SSE3-NEXT: movd %eax, %xmm1
287 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
288 ; SSE3-NEXT: andl $15, %eax
289 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
290 ; SSE3-NEXT: movd %eax, %xmm2
291 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
292 ; SSE3-NEXT: andl $15, %eax
293 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
294 ; SSE3-NEXT: movd %eax, %xmm0
295 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm8[0],xmm15[1],xmm8[1],xmm15[2],xmm8[2],xmm15[3],xmm8[3],xmm15[4],xmm8[4],xmm15[5],xmm8[5],xmm15[6],xmm8[6],xmm15[7],xmm8[7]
296 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[1],xmm3[2],xmm9[2],xmm3[3],xmm9[3],xmm3[4],xmm9[4],xmm3[5],xmm9[5],xmm3[6],xmm9[6],xmm3[7],xmm9[7]
297 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm15[0],xmm3[1],xmm15[1],xmm3[2],xmm15[2],xmm3[3],xmm15[3]
298 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm10[0],xmm7[1],xmm10[1],xmm7[2],xmm10[2],xmm7[3],xmm10[3],xmm7[4],xmm10[4],xmm7[5],xmm10[5],xmm7[6],xmm10[6],xmm7[7],xmm10[7]
299 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm11[0],xmm6[1],xmm11[1],xmm6[2],xmm11[2],xmm6[3],xmm11[3],xmm6[4],xmm11[4],xmm6[5],xmm11[5],xmm6[6],xmm11[6],xmm6[7],xmm11[7]
300 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1],xmm6[2],xmm7[2],xmm6[3],xmm7[3]
301 ; SSE3-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm3[0],xmm6[1],xmm3[1]
302 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm12[0],xmm5[1],xmm12[1],xmm5[2],xmm12[2],xmm5[3],xmm12[3],xmm5[4],xmm12[4],xmm5[5],xmm12[5],xmm5[6],xmm12[6],xmm5[7],xmm12[7]
303 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm13[0],xmm4[1],xmm13[1],xmm4[2],xmm13[2],xmm4[3],xmm13[3],xmm4[4],xmm13[4],xmm4[5],xmm13[5],xmm4[6],xmm13[6],xmm4[7],xmm13[7]
304 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1],xmm4[2],xmm5[2],xmm4[3],xmm5[3]
305 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],xmm14[1],xmm1[2],xmm14[2],xmm1[3],xmm14[3],xmm1[4],xmm14[4],xmm1[5],xmm14[5],xmm1[6],xmm14[6],xmm1[7],xmm14[7]
306 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
307 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
308 ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
309 ; SSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm6[0]
310 ; SSE3-NEXT: retq
311 ;
312 ; SSSE3-LABEL: var_shuffle_v16i8:
313 ; SSSE3: # %bb.0:
314 ; SSSE3-NEXT: pshufb %xmm1, %xmm0
315 ; SSSE3-NEXT: retq
316 ;
317 ; SSE41-LABEL: var_shuffle_v16i8:
318 ; SSE41: # %bb.0:
319 ; SSE41-NEXT: pshufb %xmm1, %xmm0
320 ; SSE41-NEXT: retq
143321 ;
144322 ; AVX-LABEL: var_shuffle_v16i8:
145323 ; AVX: # %bb.0:
197375 }
198376
199377 define <2 x double> @var_shuffle_v2f64(<2 x double> %v, <2 x i64> %indices) nounwind {
378 ; SSE3-LABEL: var_shuffle_v2f64:
379 ; SSE3: # %bb.0:
380 ; SSE3-NEXT: movq %xmm1, %rax
381 ; SSE3-NEXT: andl $1, %eax
382 ; SSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
383 ; SSE3-NEXT: movq %xmm1, %rcx
384 ; SSE3-NEXT: andl $1, %ecx
385 ; SSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
386 ; SSE3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
387 ; SSE3-NEXT: movhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
388 ; SSE3-NEXT: retq
389 ;
200390 ; SSSE3-LABEL: var_shuffle_v2f64:
201391 ; SSSE3: # %bb.0:
202392 ; SSSE3-NEXT: movq %xmm1, %rax
235425 }
236426
237427 define <4 x float> @var_shuffle_v4f32(<4 x float> %v, <4 x i32> %indices) nounwind {
428 ; SSE3-LABEL: var_shuffle_v4f32:
429 ; SSE3: # %bb.0:
430 ; SSE3-NEXT: movd %xmm1, %eax
431 ; SSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,2,3]
432 ; SSE3-NEXT: movd %xmm2, %ecx
433 ; SSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
434 ; SSE3-NEXT: movd %xmm2, %edx
435 ; SSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,1,2,3]
436 ; SSE3-NEXT: movd %xmm1, %esi
437 ; SSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
438 ; SSE3-NEXT: andl $3, %eax
439 ; SSE3-NEXT: andl $3, %ecx
440 ; SSE3-NEXT: andl $3, %edx
441 ; SSE3-NEXT: andl $3, %esi
442 ; SSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
443 ; SSE3-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
444 ; SSE3-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
445 ; SSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
446 ; SSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
447 ; SSE3-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
448 ; SSE3-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
449 ; SSE3-NEXT: retq
450 ;
238451 ; SSSE3-LABEL: var_shuffle_v4f32:
239452 ; SSSE3: # %bb.0:
240453 ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [67372036,67372036,67372036,67372036]
275488 }
276489
277490 define <16 x i8> @var_shuffle_v16i8_from_v16i8_v32i8(<16 x i8> %v, <32 x i8> %indices) nounwind {
278 ; SSE-LABEL: var_shuffle_v16i8_from_v16i8_v32i8:
279 ; SSE: # %bb.0:
280 ; SSE-NEXT: pshufb %xmm1, %xmm0
281 ; SSE-NEXT: retq
491 ; SSE3-LABEL: var_shuffle_v16i8_from_v16i8_v32i8:
492 ; SSE3: # %bb.0:
493 ; SSE3-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
494 ; SSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
495 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
496 ; SSE3-NEXT: andl $15, %eax
497 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
498 ; SSE3-NEXT: movd %eax, %xmm8
499 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
500 ; SSE3-NEXT: andl $15, %eax
501 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
502 ; SSE3-NEXT: movd %eax, %xmm15
503 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
504 ; SSE3-NEXT: andl $15, %eax
505 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
506 ; SSE3-NEXT: movd %eax, %xmm9
507 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
508 ; SSE3-NEXT: andl $15, %eax
509 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
510 ; SSE3-NEXT: movd %eax, %xmm3
511 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
512 ; SSE3-NEXT: andl $15, %eax
513 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
514 ; SSE3-NEXT: movd %eax, %xmm10
515 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
516 ; SSE3-NEXT: andl $15, %eax
517 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
518 ; SSE3-NEXT: movd %eax, %xmm7
519 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
520 ; SSE3-NEXT: andl $15, %eax
521 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
522 ; SSE3-NEXT: movd %eax, %xmm11
523 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
524 ; SSE3-NEXT: andl $15, %eax
525 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
526 ; SSE3-NEXT: movd %eax, %xmm6
527 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
528 ; SSE3-NEXT: andl $15, %eax
529 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
530 ; SSE3-NEXT: movd %eax, %xmm12
531 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
532 ; SSE3-NEXT: andl $15, %eax
533 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
534 ; SSE3-NEXT: movd %eax, %xmm5
535 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
536 ; SSE3-NEXT: andl $15, %eax
537 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
538 ; SSE3-NEXT: movd %eax, %xmm13
539 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
540 ; SSE3-NEXT: andl $15, %eax
541 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
542 ; SSE3-NEXT: movd %eax, %xmm4
543 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
544 ; SSE3-NEXT: andl $15, %eax
545 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
546 ; SSE3-NEXT: movd %eax, %xmm14
547 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
548 ; SSE3-NEXT: andl $15, %eax
549 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
550 ; SSE3-NEXT: movd %eax, %xmm1
551 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
552 ; SSE3-NEXT: andl $15, %eax
553 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
554 ; SSE3-NEXT: movd %eax, %xmm2
555 ; SSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
556 ; SSE3-NEXT: andl $15, %eax
557 ; SSE3-NEXT: movzbl -24(%rsp,%rax), %eax
558 ; SSE3-NEXT: movd %eax, %xmm0
559 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm8[0],xmm15[1],xmm8[1],xmm15[2],xmm8[2],xmm15[3],xmm8[3],xmm15[4],xmm8[4],xmm15[5],xmm8[5],xmm15[6],xmm8[6],xmm15[7],xmm8[7]
560 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[1],xmm3[2],xmm9[2],xmm3[3],xmm9[3],xmm3[4],xmm9[4],xmm3[5],xmm9[5],xmm3[6],xmm9[6],xmm3[7],xmm9[7]
561 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm15[0],xmm3[1],xmm15[1],xmm3[2],xmm15[2],xmm3[3],xmm15[3]
562 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm10[0],xmm7[1],xmm10[1],xmm7[2],xmm10[2],xmm7[3],xmm10[3],xmm7[4],xmm10[4],xmm7[5],xmm10[5],xmm7[6],xmm10[6],xmm7[7],xmm10[7]
563 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm11[0],xmm6[1],xmm11[1],xmm6[2],xmm11[2],xmm6[3],xmm11[3],xmm6[4],xmm11[4],xmm6[5],xmm11[5],xmm6[6],xmm11[6],xmm6[7],xmm11[7]
564 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1],xmm6[2],xmm7[2],xmm6[3],xmm7[3]
565 ; SSE3-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm3[0],xmm6[1],xmm3[1]
566 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm12[0],xmm5[1],xmm12[1],xmm5[2],xmm12[2],xmm5[3],xmm12[3],xmm5[4],xmm12[4],xmm5[5],xmm12[5],xmm5[6],xmm12[6],xmm5[7],xmm12[7]
567 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm13[0],xmm4[1],xmm13[1],xmm4[2],xmm13[2],xmm4[3],xmm13[3],xmm4[4],xmm13[4],xmm4[5],xmm13[5],xmm4[6],xmm13[6],xmm4[7],xmm13[7]
568 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1],xmm4[2],xmm5[2],xmm4[3],xmm5[3]
569 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],xmm14[1],xmm1[2],xmm14[2],xmm1[3],xmm14[3],xmm1[4],xmm14[4],xmm1[5],xmm14[5],xmm1[6],xmm14[6],xmm1[7],xmm14[7]
570 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
571 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
572 ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
573 ; SSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm6[0]
574 ; SSE3-NEXT: retq
575 ;
576 ; SSSE3-LABEL: var_shuffle_v16i8_from_v16i8_v32i8:
577 ; SSSE3: # %bb.0:
578 ; SSSE3-NEXT: pshufb %xmm1, %xmm0
579 ; SSSE3-NEXT: retq
580 ;
581 ; SSE41-LABEL: var_shuffle_v16i8_from_v16i8_v32i8:
582 ; SSE41: # %bb.0:
583 ; SSE41-NEXT: pshufb %xmm1, %xmm0
584 ; SSE41-NEXT: retq
282585 ;
283586 ; AVX-LABEL: var_shuffle_v16i8_from_v16i8_v32i8:
284587 ; AVX: # %bb.0:
337640 }
338641
339642 define <16 x i8> @var_shuffle_v16i8_from_v32i8_v16i8(<32 x i8> %v, <16 x i8> %indices) nounwind {
643 ; SSE3-LABEL: var_shuffle_v16i8_from_v32i8_v16i8:
644 ; SSE3: # %bb.0:
645 ; SSE3-NEXT: pushq %rbp
646 ; SSE3-NEXT: movq %rsp, %rbp
647 ; SSE3-NEXT: pushq %r15
648 ; SSE3-NEXT: pushq %r14
649 ; SSE3-NEXT: pushq %r13
650 ; SSE3-NEXT: pushq %r12
651 ; SSE3-NEXT: pushq %rbx
652 ; SSE3-NEXT: andq $-32, %rsp
653 ; SSE3-NEXT: subq $608, %rsp # imm = 0x260
654 ; SSE3-NEXT: movaps %xmm2, {{[0-9]+}}(%rsp)
655 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
656 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
657 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
658 ; SSE3-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill
659 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
660 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
661 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
662 ; SSE3-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill
663 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
664 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
665 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
666 ; SSE3-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill
667 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
668 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
669 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d
670 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
671 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
672 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %r14d
673 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
674 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
675 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %r15d
676 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
677 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
678 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %r12d
679 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
680 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
681 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %r13d
682 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
683 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
684 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d
685 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
686 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
687 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %r8d
688 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
689 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
690 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edi
691 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
692 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
693 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %esi
694 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
695 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
696 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
697 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
698 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
699 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
700 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
701 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
702 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
703 ; SSE3-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
704 ; SSE3-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
705 ; SSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %r9d
706 ; SSE3-NEXT: andl $31, %r9d
707 ; SSE3-NEXT: movzbl 64(%rsp,%r9), %ebx
708 ; SSE3-NEXT: movd %ebx, %xmm8
709 ; SSE3-NEXT: andl $31, %eax
710 ; SSE3-NEXT: movzbl 96(%rsp,%rax), %eax
711 ; SSE3-NEXT: movd %eax, %xmm15
712 ; SSE3-NEXT: andl $31, %edx
713 ; SSE3-NEXT: movzbl 128(%rsp,%rdx), %eax
714 ; SSE3-NEXT: movd %eax, %xmm9
715 ; SSE3-NEXT: andl $31, %ecx
716 ; SSE3-NEXT: movzbl 160(%rsp,%rcx), %eax
717 ; SSE3-NEXT: movd %eax, %xmm3
718 ; SSE3-NEXT: andl $31, %esi
719 ; SSE3-NEXT: movzbl 192(%rsp,%rsi), %eax
720 ; SSE3-NEXT: movd %eax, %xmm10
721 ; SSE3-NEXT: andl $31, %edi
722 ; SSE3-NEXT: movzbl 224(%rsp,%rdi), %eax
723 ; SSE3-NEXT: movd %eax, %xmm7
724 ; SSE3-NEXT: andl $31, %r8d
725 ; SSE3-NEXT: movzbl 256(%rsp,%r8), %eax
726 ; SSE3-NEXT: movd %eax, %xmm11
727 ; SSE3-NEXT: andl $31, %r10d
728 ; SSE3-NEXT: movzbl 288(%rsp,%r10), %eax
729 ; SSE3-NEXT: movd %eax, %xmm6
730 ; SSE3-NEXT: andl $31, %r13d
731 ; SSE3-NEXT: movzbl 320(%rsp,%r13), %eax
732 ; SSE3-NEXT: movd %eax, %xmm12
733 ; SSE3-NEXT: andl $31, %r12d
734 ; SSE3-NEXT: movzbl 352(%rsp,%r12), %eax
735 ; SSE3-NEXT: movd %eax, %xmm5
736 ; SSE3-NEXT: andl $31, %r15d
737 ; SSE3-NEXT: movzbl 384(%rsp,%r15), %eax
738 ; SSE3-NEXT: movd %eax, %xmm13
739 ; SSE3-NEXT: andl $31, %r14d
740 ; SSE3-NEXT: movzbl 416(%rsp,%r14), %eax
741 ; SSE3-NEXT: movd %eax, %xmm4
742 ; SSE3-NEXT: andl $31, %r11d
743 ; SSE3-NEXT: movzbl 448(%rsp,%r11), %eax
744 ; SSE3-NEXT: movd %eax, %xmm14
745 ; SSE3-NEXT: movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload
746 ; SSE3-NEXT: andl $31, %eax
747 ; SSE3-NEXT: movzbl 480(%rsp,%rax), %eax
748 ; SSE3-NEXT: movd %eax, %xmm1
749 ; SSE3-NEXT: movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload
750 ; SSE3-NEXT: andl $31, %eax
751 ; SSE3-NEXT: movzbl 512(%rsp,%rax), %eax
752 ; SSE3-NEXT: movd %eax, %xmm2
753 ; SSE3-NEXT: movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload
754 ; SSE3-NEXT: andl $31, %eax
755 ; SSE3-NEXT: movzbl 544(%rsp,%rax), %eax
756 ; SSE3-NEXT: movd %eax, %xmm0
757 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm8[0],xmm15[1],xmm8[1],xmm15[2],xmm8[2],xmm15[3],xmm8[3],xmm15[4],xmm8[4],xmm15[5],xmm8[5],xmm15[6],xmm8[6],xmm15[7],xmm8[7]
758 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[1],xmm3[2],xmm9[2],xmm3[3],xmm9[3],xmm3[4],xmm9[4],xmm3[5],xmm9[5],xmm3[6],xmm9[6],xmm3[7],xmm9[7]
759 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm15[0],xmm3[1],xmm15[1],xmm3[2],xmm15[2],xmm3[3],xmm15[3]
760 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm10[0],xmm7[1],xmm10[1],xmm7[2],xmm10[2],xmm7[3],xmm10[3],xmm7[4],xmm10[4],xmm7[5],xmm10[5],xmm7[6],xmm10[6],xmm7[7],xmm10[7]
761 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm11[0],xmm6[1],xmm11[1],xmm6[2],xmm11[2],xmm6[3],xmm11[3],xmm6[4],xmm11[4],xmm6[5],xmm11[5],xmm6[6],xmm11[6],xmm6[7],xmm11[7]
762 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1],xmm6[2],xmm7[2],xmm6[3],xmm7[3]
763 ; SSE3-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm3[0],xmm6[1],xmm3[1]
764 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm12[0],xmm5[1],xmm12[1],xmm5[2],xmm12[2],xmm5[3],xmm12[3],xmm5[4],xmm12[4],xmm5[5],xmm12[5],xmm5[6],xmm12[6],xmm5[7],xmm12[7]
765 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm13[0],xmm4[1],xmm13[1],xmm4[2],xmm13[2],xmm4[3],xmm13[3],xmm4[4],xmm13[4],xmm4[5],xmm13[5],xmm4[6],xmm13[6],xmm4[7],xmm13[7]
766 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1],xmm4[2],xmm5[2],xmm4[3],xmm5[3]
767 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],xmm14[1],xmm1[2],xmm14[2],xmm1[3],xmm14[3],xmm1[4],xmm14[4],xmm1[5],xmm14[5],xmm1[6],xmm14[6],xmm1[7],xmm14[7]
768 ; SSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
769 ; SSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
770 ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
771 ; SSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm6[0]
772 ; SSE3-NEXT: leaq -40(%rbp), %rsp
773 ; SSE3-NEXT: popq %rbx
774 ; SSE3-NEXT: popq %r12
775 ; SSE3-NEXT: popq %r13
776 ; SSE3-NEXT: popq %r14
777 ; SSE3-NEXT: popq %r15
778 ; SSE3-NEXT: popq %rbp
779 ; SSE3-NEXT: retq
780 ;
340781 ; SSSE3-LABEL: var_shuffle_v16i8_from_v32i8_v16i8:
341782 ; SSSE3: # %bb.0:
342783 ; SSSE3-NEXT: pushq %rbp