llvm.org GIT mirror llvm / 3d3e407
[C++11] Add 'override' keyword to virtual methods that override their base class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203439 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 6 years ago
10 changed file(s) with 120 addition(s) and 121 deletion(s). Raw diff Collapse all Expand all
358358 }
359359
360360 // Implementation of the MCTargetAsmParser interface:
361 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
362 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
363 SMLoc NameLoc,
364 SmallVectorImpl &Operands);
365 bool ParseDirective(AsmToken DirectiveID);
366
367 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
368 unsigned checkTargetMatchPredicate(MCInst &Inst);
361 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
362 bool
363 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
364 SMLoc NameLoc,
365 SmallVectorImpl &Operands) override;
366 bool ParseDirective(AsmToken DirectiveID) override;
367
368 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
369 unsigned Kind) override;
370 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
369371
370372 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
371373 SmallVectorImpl &Operands,
372374 MCStreamer &Out, unsigned &ErrorInfo,
373 bool MatchingInlineAsm);
374 void onLabelParsed(MCSymbol *Symbol);
375 bool MatchingInlineAsm) override;
376 void onLabelParsed(MCSymbol *Symbol) override;
375377 };
376378 } // end anonymous namespace
377379
620622 }
621623
622624 /// getStartLoc - Get the location of the first token of this operand.
623 SMLoc getStartLoc() const { return StartLoc; }
625 SMLoc getStartLoc() const override { return StartLoc; }
624626 /// getEndLoc - Get the location of the last token of this operand.
625 SMLoc getEndLoc() const { return EndLoc; }
627 SMLoc getEndLoc() const override { return EndLoc; }
626628 /// getLocRange - Get the range between the first and last token of this
627629 /// operand.
628630 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
642644 return StringRef(Tok.Data, Tok.Length);
643645 }
644646
645 unsigned getReg() const {
647 unsigned getReg() const override {
646648 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
647649 return Reg.RegNum;
648650 }
690692 bool isCCOut() const { return Kind == k_CCOut; }
691693 bool isITMask() const { return Kind == k_ITCondMask; }
692694 bool isITCondCode() const { return Kind == k_CondCode; }
693 bool isImm() const { return Kind == k_Immediate; }
695 bool isImm() const override { return Kind == k_Immediate; }
694696 // checks whether this operand is an unsigned offset which fits is a field
695697 // of specified width and scaled by a specific number of bits
696698 template
10661068 int64_t Value = CE->getValue();
10671069 return Value == 1 || Value == 0;
10681070 }
1069 bool isReg() const { return Kind == k_Register; }
1071 bool isReg() const override { return Kind == k_Register; }
10701072 bool isRegList() const { return Kind == k_RegisterList; }
10711073 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
10721074 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1073 bool isToken() const { return Kind == k_Token; }
1075 bool isToken() const override { return Kind == k_Token; }
10741076 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
10751077 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1076 bool isMem() const { return Kind == k_Memory; }
1078 bool isMem() const override { return Kind == k_Memory; }
10771079 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
10781080 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
10791081 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
23082310 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
23092311 }
23102312
2311 virtual void print(raw_ostream &OS) const;
2313 void print(raw_ostream &OS) const override;
23122314
23132315 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
23142316 ARMOperand *Op = new ARMOperand(k_ITCondMask);
9797 }
9898
9999 /// getInstruction - See MCDisassembler.
100 DecodeStatus getInstruction(MCInst &instr,
101 uint64_t &size,
102 const MemoryObject ®ion,
103 uint64_t address,
100 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
101 const MemoryObject ®ion, uint64_t address,
104102 raw_ostream &vStream,
105 raw_ostream &cStream) const;
103 raw_ostream &cStream) const override;
106104 };
107105
108106 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
118116 }
119117
120118 /// getInstruction - See MCDisassembler.
121 DecodeStatus getInstruction(MCInst &instr,
122 uint64_t &size,
123 const MemoryObject ®ion,
124 uint64_t address,
119 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
120 const MemoryObject ®ion, uint64_t address,
125121 raw_ostream &vStream,
126 raw_ostream &cStream) const;
122 raw_ostream &cStream) const override;
127123
128124 private:
129125 mutable ITStatus ITBlock;
5050 delete STI;
5151 }
5252
53 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
53 unsigned getNumFixupKinds() const override {
54 return ARM::NumTargetFixupKinds;
55 }
5456
5557 bool hasNOP() const {
5658 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
5759 }
5860
59 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
61 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
6062 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
6163 // This table *must* be in the order that the fixup_* kinds are defined in
6264 // ARMFixupKinds.h.
112114 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
113115 const MCFixup &Fixup, const MCFragment *DF,
114116 MCValue &Target, uint64_t &Value,
115 bool &IsResolved);
117 bool &IsResolved) override;
116118
117119
118120 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
119 uint64_t Value) const;
120
121 bool mayNeedRelaxation(const MCInst &Inst) const;
122
123 bool fixupNeedsRelaxation(const MCFixup &Fixup,
124 uint64_t Value,
121 uint64_t Value) const override;
122
123 bool mayNeedRelaxation(const MCInst &Inst) const override;
124
125 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
125126 const MCRelaxableFragment *DF,
126 const MCAsmLayout &Layout) const;
127
128 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
129
130 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
131
132 void handleAssemblerFlag(MCAssemblerFlag Flag) {
127 const MCAsmLayout &Layout) const override;
128
129 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override;
130
131 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
132
133 void handleAssemblerFlag(MCAssemblerFlag Flag) override {
133134 switch (Flag) {
134135 default: break;
135136 case MCAF_Code16:
662663 uint8_t _OSABI)
663664 : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
664665
665 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
666 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
666667 return createARMELFObjectWriter(OS, OSABI);
667668 }
668669 };
677678 HasDataInCodeSupport = true;
678679 }
679680
680 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
681 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
681682 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
682683 MachO::CPU_TYPE_ARM,
683684 Subtype);
3333
3434 virtual ~ARMELFObjectWriter();
3535
36 virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
37 bool IsPCRel, bool IsRelocWithSymbol,
38 int64_t Addend) const;
39 virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm,
40 const MCValue &Target,
41 const MCFragment &F,
36 unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
37 bool IsPCRel, bool IsRelocWithSymbol,
38 int64_t Addend) const override;
39 const MCSymbol *ExplicitRelSym(const MCAssembler &Asm,
40 const MCValue &Target, const MCFragment &F,
4241 const MCFixup &Fixup,
43 bool IsPCRel) const;
42 bool IsPCRel) const override;
4443 };
4544 }
4645
113113 MCInstPrinter &InstPrinter;
114114 bool IsVerboseAsm;
115115
116 virtual void emitFnStart();
117 virtual void emitFnEnd();
118 virtual void emitCantUnwind();
119 virtual void emitPersonality(const MCSymbol *Personality);
120 virtual void emitPersonalityIndex(unsigned Index);
121 virtual void emitHandlerData();
122 virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0);
123 virtual void emitMovSP(unsigned Reg, int64_t Offset = 0);
124 virtual void emitPad(int64_t Offset);
125 virtual void emitRegSave(const SmallVectorImpl &RegList,
126 bool isVector);
127 virtual void emitUnwindRaw(int64_t Offset,
128 const SmallVectorImpl &Opcodes);
129
130 virtual void switchVendor(StringRef Vendor);
131 virtual void emitAttribute(unsigned Attribute, unsigned Value);
132 virtual void emitTextAttribute(unsigned Attribute, StringRef String);
133 virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
134 StringRef StrinValue);
135 virtual void emitArch(unsigned Arch);
136 virtual void emitObjectArch(unsigned Arch);
137 virtual void emitFPU(unsigned FPU);
138 virtual void emitInst(uint32_t Inst, char Suffix = '\0');
139 virtual void finishAttributeSection();
140
141 virtual void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE);
116 void emitFnStart() override;
117 void emitFnEnd() override;
118 void emitCantUnwind() override;
119 void emitPersonality(const MCSymbol *Personality) override;
120 void emitPersonalityIndex(unsigned Index) override;
121 void emitHandlerData() override;
122 void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0) override;
123 void emitMovSP(unsigned Reg, int64_t Offset = 0) override;
124 void emitPad(int64_t Offset) override;
125 void emitRegSave(const SmallVectorImpl &RegList,
126 bool isVector) override;
127 void emitUnwindRaw(int64_t Offset,
128 const SmallVectorImpl &Opcodes) override;
129
130 void switchVendor(StringRef Vendor) override;
131 void emitAttribute(unsigned Attribute, unsigned Value) override;
132 void emitTextAttribute(unsigned Attribute, StringRef String) override;
133 void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
134 StringRef StrinValue) override;
135 void emitArch(unsigned Arch) override;
136 void emitObjectArch(unsigned Arch) override;
137 void emitFPU(unsigned FPU) override;
138 void emitInst(uint32_t Inst, char Suffix = '\0') override;
139 void finishAttributeSection() override;
140
141 void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) override;
142142
143143 public:
144144 ARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS,
382382
383383 ARMELFStreamer &getStreamer();
384384
385 virtual void emitFnStart();
386 virtual void emitFnEnd();
387 virtual void emitCantUnwind();
388 virtual void emitPersonality(const MCSymbol *Personality);
389 virtual void emitPersonalityIndex(unsigned Index);
390 virtual void emitHandlerData();
391 virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0);
392 virtual void emitMovSP(unsigned Reg, int64_t Offset = 0);
393 virtual void emitPad(int64_t Offset);
394 virtual void emitRegSave(const SmallVectorImpl &RegList,
395 bool isVector);
396 virtual void emitUnwindRaw(int64_t Offset,
397 const SmallVectorImpl &Opcodes);
398
399 virtual void switchVendor(StringRef Vendor);
400 virtual void emitAttribute(unsigned Attribute, unsigned Value);
401 virtual void emitTextAttribute(unsigned Attribute, StringRef String);
402 virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
403 StringRef StringValue);
404 virtual void emitArch(unsigned Arch);
405 virtual void emitObjectArch(unsigned Arch);
406 virtual void emitFPU(unsigned FPU);
407 virtual void emitInst(uint32_t Inst, char Suffix = '\0');
408 virtual void finishAttributeSection();
409
410 virtual void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE);
385 void emitFnStart() override;
386 void emitFnEnd() override;
387 void emitCantUnwind() override;
388 void emitPersonality(const MCSymbol *Personality) override;
389 void emitPersonalityIndex(unsigned Index) override;
390 void emitHandlerData() override;
391 void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0) override;
392 void emitMovSP(unsigned Reg, int64_t Offset = 0) override;
393 void emitPad(int64_t Offset) override;
394 void emitRegSave(const SmallVectorImpl &RegList,
395 bool isVector) override;
396 void emitUnwindRaw(int64_t Offset,
397 const SmallVectorImpl &Opcodes) override;
398
399 void switchVendor(StringRef Vendor) override;
400 void emitAttribute(unsigned Attribute, unsigned Value) override;
401 void emitTextAttribute(unsigned Attribute, StringRef String) override;
402 void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
403 StringRef StringValue) override;
404 void emitArch(unsigned Arch) override;
405 void emitObjectArch(unsigned Arch) override;
406 void emitFPU(unsigned FPU) override;
407 void emitInst(uint32_t Inst, char Suffix = '\0') override;
408 void finishAttributeSection() override;
409
410 void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) override;
411411
412412 size_t calculateContentSize() const;
413413
443443
444444 ~ARMELFStreamer() {}
445445
446 virtual void FinishImpl();
446 void FinishImpl() override;
447447
448448 // ARM exception handling directives
449449 void emitFnStart();
458458 void emitRegSave(const SmallVectorImpl &RegList, bool isVector);
459459 void emitUnwindRaw(int64_t Offset, const SmallVectorImpl &Opcodes);
460460
461 virtual void ChangeSection(const MCSection *Section,
462 const MCExpr *Subsection) {
461 void ChangeSection(const MCSection *Section,
462 const MCExpr *Subsection) override {
463463 // We have to keep track of the mapping symbol state of any sections we
464464 // use. Each one should start off as EMS_None, which is provided as the
465465 // default constructor by DenseMap::lookup.
472472 /// This function is the one used to emit instruction data into the ELF
473473 /// streamer. We override it to add the appropriate mapping symbol if
474474 /// necessary.
475 virtual void EmitInstruction(const MCInst& Inst, const MCSubtargetInfo &STI) {
475 void EmitInstruction(const MCInst& Inst,
476 const MCSubtargetInfo &STI) override {
476477 if (IsThumb)
477478 EmitThumbMappingSymbol();
478479 else
522523 /// This is one of the functions used to emit data into an ELF section, so the
523524 /// ARM streamer overrides it to add the appropriate mapping symbol ($d) if
524525 /// necessary.
525 virtual void EmitBytes(StringRef Data) {
526 void EmitBytes(StringRef Data) override {
526527 EmitDataMappingSymbol();
527528 MCELFStreamer::EmitBytes(Data);
528529 }
530531 /// This is one of the functions used to emit data into an ELF section, so the
531532 /// ARM streamer overrides it to add the appropriate mapping symbol ($d) if
532533 /// necessary.
533 virtual void EmitValueImpl(const MCExpr *Value, unsigned Size) {
534 void EmitValueImpl(const MCExpr *Value, unsigned Size) override {
534535 EmitDataMappingSymbol();
535536 MCELFStreamer::EmitValueImpl(Value, Size);
536537 }
537538
538 virtual void EmitAssemblerFlag(MCAssemblerFlag Flag) {
539 void EmitAssemblerFlag(MCAssemblerFlag Flag) override {
539540 MCELFStreamer::EmitAssemblerFlag(Flag);
540541
541542 switch (Flag) {
598599 Symbol->setVariableValue(Value);
599600 }
600601
601 void EmitThumbFunc(MCSymbol *Func) {
602 void EmitThumbFunc(MCSymbol *Func) override {
602603 // FIXME: Anything needed here to flag the function as thumb?
603604
604605 getAssembler().setIsThumbFunc(Func);
1919 namespace llvm {
2020
2121 class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin {
22 virtual void anchor();
22 void anchor() override;
2323 public:
2424 explicit ARMMCAsmInfoDarwin();
2525 };
2626
2727 class ARMELFMCAsmInfo : public MCAsmInfoELF {
28 virtual void anchor();
28 void anchor() override;
2929 public:
3030 explicit ARMELFMCAsmInfo();
3131 };
391391
392392 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
393393 SmallVectorImpl &Fixups,
394 const MCSubtargetInfo &STI) const;
394 const MCSubtargetInfo &STI) const override;
395395 };
396396
397397 } // end anonymous namespace
286286 public:
287287 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
288288
289 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
289 bool isUnconditionalBranch(const MCInst &Inst) const override {
290290 // BCCs with the "always" predicate are unconditional branches.
291291 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
292292 return true;
293293 return MCInstrAnalysis::isUnconditionalBranch(Inst);
294294 }
295295
296 virtual bool isConditionalBranch(const MCInst &Inst) const {
296 bool isConditionalBranch(const MCInst &Inst) const override {
297297 // BCCs with the "always" predicate are unconditional branches.
298298 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
299299 return false;
301301 }
302302
303303 bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
304 uint64_t Size, uint64_t &Target) const {
304 uint64_t Size, uint64_t &Target) const override {
305305 // We only handle PCRel branches for now.
306306 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
307307 return false;
2222 ARMMachORelocationInfo(MCContext &Ctx) : MCRelocationInfo(Ctx) {}
2323
2424 const MCExpr *createExprForCAPIVariantKind(const MCExpr *SubExpr,
25 unsigned VariantKind) {
25 unsigned VariantKind) override {
2626 switch(VariantKind) {
2727 case LLVMDisassembler_VariantKind_ARM_HI16:
2828 return ARMMCExpr::CreateUpper16(SubExpr, Ctx);
5555 void RecordRelocation(MachObjectWriter *Writer,
5656 const MCAssembler &Asm, const MCAsmLayout &Layout,
5757 const MCFragment *Fragment, const MCFixup &Fixup,
58 MCValue Target, uint64_t &FixedValue);
58 MCValue Target, uint64_t &FixedValue) override;
5959 };
6060 }
6161