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Merging r324581: ------------------------------------------------------------------------ r324581 | sjoerdmeijer | 2018-02-08 00:39:05 -0800 (Thu, 08 Feb 2018) | 12 lines [AArch64] Don't materialize 0 with "fmov h0, .." when FullFP16 is not supported We were generating "fmov h0, wzr" instructions when FullFP16 is not enabled. I've not added any tests, because the problem was visible in: test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll, which I had to change: I don't think Cyclone has FullFP16 enabled by default, so it shouldn't be using this v8.2a instruction. I've also removed these rdar tags, please shout if there are any objections. Differential Revision: https://reviews.llvm.org/D43020 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@332655 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 5 months ago
3 changed file(s) with 11 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
49294929 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
49304930 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
49314931 // FIXME: We should be able to handle f128 as well with a clever lowering.
4932 if (Imm.isPosZero() && (VT == MVT::f16 || VT == MVT::f64 || VT == MVT::f32)) {
4932 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32 ||
4933 (VT == MVT::f16 && Subtarget->hasFullFP16()))) {
49334934 DEBUG(dbgs() << "Legal fp imm: materialize 0 using the zero register\n");
49344935 return true;
49354936 }
27122712 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
27132713 let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in {
27142714 def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>,
2715 Sched<[WriteF]>;
2715 Sched<[WriteF]>, Requires<[HasFullFP16]>;
27162716 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
27172717 Sched<[WriteF]>;
27182718 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
0 ; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s -check-prefixes=ALL,CYCLONE
1 ; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone -mattr=+fullfp16 < %s | FileCheck %s -check-prefixes=CYCLONE-FULLFP16
12 ; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m1 < %s | FileCheck %s -check-prefixes=ALL,OTHERS
23 ; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m3 < %s | FileCheck %s -check-prefixes=ALL,OTHERS
34 ; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=kryo < %s | FileCheck %s -check-prefixes=ALL,OTHERS
45 ; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=falkor < %s | FileCheck %s -check-prefixes=ALL,OTHERS
5
6 ; rdar://11481771
7 ; rdar://13713797
86
97 declare void @bar(half, float, double, <2 x double>)
108 declare void @bari(i32, i32)
1513 entry:
1614 ; ALL-LABEL: t1:
1715 ; ALL-NOT: fmov
18 ; CYCLONE: fmov h0, wzr
16 ; ALL: ldr h0,{{.*}}
1917 ; CYCLONE: fmov s1, wzr
2018 ; CYCLONE: fmov d2, xzr
2119 ; CYCLONE: movi.16b v3, #0
22 ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
20 ; CYCLONE-FULLFP16: fmov h0, wzr
21 ; CYCLONE-FULLFP16: fmov s1, wzr
22 ; CYCLONE-FULLFP16: fmov d2, xzr
23 ; CYCLONE-FULLFP16: movi.16b v3, #0
2324 ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
2425 ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
2526 ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
5253 ; ALL-NOT: fmov
5354 ; CYCLONE: fmov s{{[0-3]+}}, wzr
5455 ; CYCLONE: fmov s{{[0-3]+}}, wzr
56 ; CYCLONE-FULLFP16: fmov s{{[0-3]+}}, wzr
57 ; CYCLONE-FULLFP16: fmov s{{[0-3]+}}, wzr
5558 ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
5659 ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
5760 tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind