llvm.org GIT mirror llvm / 3d1f75a
Rename the isMemory() function to isMem(). No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163654 91177308-0d34-0410-b5e6-96231b3b80d8 Chad Rosier 7 years ago
1 changed file(s) with 22 addition(s) and 22 deletion(s). Raw diff Collapse all Expand all
862862 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
863863 bool isToken() const { return Kind == k_Token; }
864864 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
865 bool isMemory() const { return Kind == k_Memory; }
865 bool isMem() const { return Kind == k_Memory; }
866866 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
867867 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
868868 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
873873 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
874874 }
875875 bool isMemNoOffset(bool alignOK = false) const {
876 if (!isMemory())
876 if (!isMem())
877877 return false;
878878 // No offset of any kind.
879879 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
880880 (alignOK || Memory.Alignment == 0);
881881 }
882882 bool isMemPCRelImm12() const {
883 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
883 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
884884 return false;
885885 // Base register must be PC.
886886 if (Memory.BaseRegNum != ARM::PC)
894894 return isMemNoOffset(true);
895895 }
896896 bool isAddrMode2() const {
897 if (!isMemory() || Memory.Alignment != 0) return false;
897 if (!isMem() || Memory.Alignment != 0) return false;
898898 // Check for register offset.
899899 if (Memory.OffsetRegNum) return true;
900900 // Immediate offset in range [-4095, 4095].
916916 // and we reject it.
917917 if (isImm() && !isa(getImm()))
918918 return true;
919 if (!isMemory() || Memory.Alignment != 0) return false;
919 if (!isMem() || Memory.Alignment != 0) return false;
920920 // No shifts are legal for AM3.
921921 if (Memory.ShiftType != ARM_AM::no_shift) return false;
922922 // Check for register offset.
946946 // and we reject it.
947947 if (isImm() && !isa(getImm()))
948948 return true;
949 if (!isMemory() || Memory.Alignment != 0) return false;
949 if (!isMem() || Memory.Alignment != 0) return false;
950950 // Check for register offset.
951951 if (Memory.OffsetRegNum) return false;
952952 // Immediate offset in range [-1020, 1020] and a multiple of 4.
956956 Val == INT32_MIN;
957957 }
958958 bool isMemTBB() const {
959 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
959 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
960960 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
961961 return false;
962962 return true;
963963 }
964964 bool isMemTBH() const {
965 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
965 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
966966 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
967967 Memory.Alignment != 0 )
968968 return false;
969969 return true;
970970 }
971971 bool isMemRegOffset() const {
972 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
972 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
973973 return false;
974974 return true;
975975 }
976976 bool isT2MemRegOffset() const {
977 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
977 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
978978 Memory.Alignment != 0)
979979 return false;
980980 // Only lsl #{0, 1, 2, 3} allowed.
987987 bool isMemThumbRR() const {
988988 // Thumb reg+reg addressing is simple. Just two registers, a base and
989989 // an offset. No shifts, negations or any other complicating factors.
990 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
990 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
991991 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
992992 return false;
993993 return isARMLowRegister(Memory.BaseRegNum) &&
994994 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
995995 }
996996 bool isMemThumbRIs4() const {
997 if (!isMemory() || Memory.OffsetRegNum != 0 ||
997 if (!isMem() || Memory.OffsetRegNum != 0 ||
998998 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
999999 return false;
10001000 // Immediate offset, multiple of 4 in range [0, 124].
10031003 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
10041004 }
10051005 bool isMemThumbRIs2() const {
1006 if (!isMemory() || Memory.OffsetRegNum != 0 ||
1006 if (!isMem() || Memory.OffsetRegNum != 0 ||
10071007 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
10081008 return false;
10091009 // Immediate offset, multiple of 4 in range [0, 62].
10121012 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
10131013 }
10141014 bool isMemThumbRIs1() const {
1015 if (!isMemory() || Memory.OffsetRegNum != 0 ||
1015 if (!isMem() || Memory.OffsetRegNum != 0 ||
10161016 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
10171017 return false;
10181018 // Immediate offset in range [0, 31].
10211021 return Val >= 0 && Val <= 31;
10221022 }
10231023 bool isMemThumbSPI() const {
1024 if (!isMemory() || Memory.OffsetRegNum != 0 ||
1024 if (!isMem() || Memory.OffsetRegNum != 0 ||
10251025 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
10261026 return false;
10271027 // Immediate offset, multiple of 4 in range [0, 1020].
10351035 // and we reject it.
10361036 if (isImm() && !isa(getImm()))
10371037 return true;
1038 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1038 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
10391039 return false;
10401040 // Immediate offset a multiple of 4 in range [-1020, 1020].
10411041 if (!Memory.OffsetImm) return true;
10441044 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
10451045 }
10461046 bool isMemImm0_1020s4Offset() const {
1047 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1047 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
10481048 return false;
10491049 // Immediate offset a multiple of 4 in range [0, 1020].
10501050 if (!Memory.OffsetImm) return true;
10521052 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
10531053 }
10541054 bool isMemImm8Offset() const {
1055 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1055 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
10561056 return false;
10571057 // Base reg of PC isn't allowed for these encodings.
10581058 if (Memory.BaseRegNum == ARM::PC) return false;
10621062 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
10631063 }
10641064 bool isMemPosImm8Offset() const {
1065 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1065 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
10661066 return false;
10671067 // Immediate offset in range [0, 255].
10681068 if (!Memory.OffsetImm) return true;
10701070 return Val >= 0 && Val < 256;
10711071 }
10721072 bool isMemNegImm8Offset() const {
1073 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1073 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
10741074 return false;
10751075 // Base reg of PC isn't allowed for these encodings.
10761076 if (Memory.BaseRegNum == ARM::PC) return false;
10801080 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
10811081 }
10821082 bool isMemUImm12Offset() const {
1083 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1083 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
10841084 return false;
10851085 // Immediate offset in range [0, 4095].
10861086 if (!Memory.OffsetImm) return true;
10941094 if (isImm() && !isa(getImm()))
10951095 return true;
10961096
1097 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1097 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
10981098 return false;
10991099 // Immediate offset in range [-4095, 4095].
11001100 if (!Memory.OffsetImm) return true;