llvm.org GIT mirror llvm / 3d1975d
[DAG] Refactor some logic. No functional change. This patch removes function 'CommuteVectorShuffle' from X86ISelLowering.cpp and moves its logic into SelectionDAG.cpp as method 'getCommutedVectorShuffles'. This refactoring is in preperation of an upcoming change to the DAGCombiner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213503 91177308-0d34-0410-b5e6-96231b3b80d8 Andrea Di Biagio 5 years ago
3 changed file(s) with 33 addition(s) and 28 deletion(s). Raw diff Collapse all Expand all
544544 "Must have the same number of vector elements as mask elements!");
545545 return getVectorShuffle(VT, dl, N1, N2, MaskElts.data());
546546 }
547
548 /// \brief Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to
549 /// the shuffle node in input but with swapped operands.
550 ///
551 /// Example: shuffle A, B, <0,5,2,7> -> shuffle B, A, <4,1,6,3>
552 SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV);
547553
548554 /// getAnyExtOrTrunc - Convert Op, which must be of integer type, to the
549555 /// integer type VT, by either any-extending or truncating it.
15951595 CSEMap.InsertNode(N, IP);
15961596 AllNodes.push_back(N);
15971597 return SDValue(N, 0);
1598 }
1599
1600 SDValue SelectionDAG::getCommutedVectorShuffle(const ShuffleVectorSDNode &SV) {
1601 MVT VT = SV.getSimpleValueType(0);
1602 unsigned NumElems = VT.getVectorNumElements();
1603 SmallVector MaskVec;
1604
1605 for (unsigned i = 0; i != NumElems; ++i) {
1606 int Idx = SV.getMaskElt(i);
1607 if (Idx >= 0) {
1608 if (Idx < (int)NumElems)
1609 Idx += NumElems;
1610 else
1611 Idx -= NumElems;
1612 }
1613 MaskVec.push_back(Idx);
1614 }
1615
1616 SDValue Op0 = SV.getOperand(0);
1617 SDValue Op1 = SV.getOperand(1);
1618 return getVectorShuffle(VT, SDLoc(&SV), Op1, Op0, &MaskVec[0]);
15981619 }
15991620
16001621 SDValue SelectionDAG::getConvertRndSat(EVT VT, SDLoc dl,
47664766 return false;
47674767 }
47684768
4769 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4770 /// their permute mask.
4771 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4772 SelectionDAG &DAG) {
4773 MVT VT = SVOp->getSimpleValueType(0);
4774 unsigned NumElems = VT.getVectorNumElements();
4775 SmallVector MaskVec;
4776
4777 for (unsigned i = 0; i != NumElems; ++i) {
4778 int Idx = SVOp->getMaskElt(i);
4779 if (Idx >= 0) {
4780 if (Idx < (int)NumElems)
4781 Idx += NumElems;
4782 else
4783 Idx -= NumElems;
4784 }
4785 MaskVec.push_back(Idx);
4786 }
4787 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4788 SVOp->getOperand(0), &MaskVec[0]);
4789 }
4790
47914769 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
47924770 /// match movhlps. The lower half elements should come from upper half of
47934771 /// V1 (and in order), and the upper half elements should come from the upper
79517929 // but in some cases the first operand may be transformed to UNDEF.
79527930 // In this case we should just commute the node.
79537931 if (V1IsUndef)
7954 return CommuteVectorShuffle(SVOp, DAG);
7932 return DAG.getCommutedVectorShuffle(*SVOp);
79557933
79567934 // Check for non-undef masks pointing at an undef vector and make the masks
79577935 // undef as well. This makes it easier to match the shuffle based solely on
79977975 // V2. This allows us to match the shuffle pattern strictly on how many
79987976 // elements come from V1 without handling the symmetric cases.
79997977 if (NumV2Elements > NumV1Elements)
8000 return CommuteVectorShuffle(SVOp, DAG);
7978 return DAG.getCommutedVectorShuffle(*SVOp);
80017979
80027980 // When the number of V1 and V2 elements are the same, try to minimize the
80037981 // number of uses of V2 in the low half of the vector.
80097987 else if (M >= 0)
80107988 ++LowV1Elements;
80117989 if (LowV2Elements > LowV1Elements)
8012 return CommuteVectorShuffle(SVOp, DAG);
7990 return DAG.getCommutedVectorShuffle(*SVOp);
80137991 }
80147992
80157993 // For each vector width, delegate to a specialized lowering routine.
92939271 // but in some cases the first operand may be transformed to UNDEF.
92949272 // In this case we should just commute the node.
92959273 if (V1IsUndef)
9296 return CommuteVectorShuffle(SVOp, DAG);
9274 return DAG.getCommutedVectorShuffle(*SVOp);
92979275
92989276 // Vector shuffle lowering takes 3 steps:
92999277 //
94059383
94069384 if (ShouldXformToMOVHLPS(M, VT) ||
94079385 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
9408 return CommuteVectorShuffle(SVOp, DAG);
9386 return DAG.getCommutedVectorShuffle(*SVOp);
94099387
94109388 if (isShift) {
94119389 // No better options. Use a vshldq / vsrldq.
94779455
94789456 // Normalize the node to match x86 shuffle ops if needed
94799457 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
9480 return CommuteVectorShuffle(SVOp, DAG);
9458 return DAG.getCommutedVectorShuffle(*SVOp);
94819459
94829460 // The checks below are all present in isShuffleMaskLegal, but they are
94839461 // inlined here right now to enable us to directly emit target specific