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[X86] Add isel patterns to match vpdpwssd avx512vnni instruction from add+pmaddwd nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369859 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 28 days ago
2 changed file(s) with 227 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
1193311933 defm VPDPWSSD : VNNI_common<0x52, "vpdpwssd", X86Vpdpwssd, SchedWriteVecIMul, 1>;
1193411934 defm VPDPWSSDS : VNNI_common<0x53, "vpdpwssds", X86Vpdpwssds, SchedWriteVecIMul, 1>;
1193511935
11936 def X86vpmaddwd_su : PatFrag<(ops node:$lhs, node:$rhs),
11937 (X86vpmaddwd node:$lhs, node:$rhs), [{
11938 return N->hasOneUse();
11939 }]>;
11940
11941 // Patterns to match VPDPWSSD from existing instructions/intrinsics.
11942 let Predicates = [HasVNNI] in {
11943 def : Pat<(v16i32 (add VR512:$src1,
11944 (X86vpmaddwd_su VR512:$src2, VR512:$src3))),
11945 (VPDPWSSDZr VR512:$src1, VR512:$src2, VR512:$src3)>;
11946 def : Pat<(v16i32 (add VR512:$src1,
11947 (X86vpmaddwd_su VR512:$src2, (load addr:$src3)))),
11948 (VPDPWSSDZm VR512:$src1, VR512:$src2, addr:$src3)>;
11949 }
11950 let Predicates = [HasVNNI,HasVLX] in {
11951 def : Pat<(v8i32 (add VR256X:$src1,
11952 (X86vpmaddwd_su VR256X:$src2, VR256X:$src3))),
11953 (VPDPWSSDZ256r VR256X:$src1, VR256X:$src2, VR256X:$src3)>;
11954 def : Pat<(v8i32 (add VR256X:$src1,
11955 (X86vpmaddwd_su VR256X:$src2, (load addr:$src3)))),
11956 (VPDPWSSDZ256m VR256X:$src1, VR256X:$src2, addr:$src3)>;
11957 def : Pat<(v4i32 (add VR128X:$src1,
11958 (X86vpmaddwd_su VR128X:$src2, VR128X:$src3))),
11959 (VPDPWSSDZ128r VR128X:$src1, VR128X:$src2, VR128X:$src3)>;
11960 def : Pat<(v4i32 (add VR128X:$src1,
11961 (X86vpmaddwd_su VR128X:$src2, (load addr:$src3)))),
11962 (VPDPWSSDZ128m VR128X:$src1, VR128X:$src2, addr:$src3)>;
11963 }
11964
1193611965 //===----------------------------------------------------------------------===//
1193711966 // Bit Algorithms
1193811967 //===----------------------------------------------------------------------===//
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni,+avx512vl,+avx512bw | FileCheck %s --check-prefixes=CHECK
2
3 define <4 x i32> @test_pmaddwd_v8i16_add_v4i32(<4 x i32> %a0, <8 x i16> %a1, <8 x i16> %a2) {
4 ; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32:
5 ; CHECK: # %bb.0:
6 ; CHECK-NEXT: vpdpwssd %xmm2, %xmm1, %xmm0
7 ; CHECK-NEXT: retq
8 %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
9 %2 = add <4 x i32> %1, %a0
10 ret <4 x i32> %2
11 }
12
13 define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_commute(<4 x i32> %a0, <8 x i16> %a1, <8 x i16> %a2) {
14 ; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_commute:
15 ; CHECK: # %bb.0:
16 ; CHECK-NEXT: vpdpwssd %xmm2, %xmm1, %xmm0
17 ; CHECK-NEXT: retq
18 %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
19 %2 = add <4 x i32> %a0, %1
20 ret <4 x i32> %2
21 }
22
23 define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_load1(<4 x i32> %a0, <8 x i16>* %p1, <8 x i16> %a2) {
24 ; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_load1:
25 ; CHECK: # %bb.0:
26 ; CHECK-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
27 ; CHECK-NEXT: retq
28 %a1 = load <8 x i16>, <8 x i16>* %p1
29 %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
30 %2 = add <4 x i32> %1, %a0
31 ret <4 x i32> %2
32 }
33
34 define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_load2(<4 x i32> %a0, <8 x i16> %a1, <8 x i16>* %p2) {
35 ; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_load2:
36 ; CHECK: # %bb.0:
37 ; CHECK-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
38 ; CHECK-NEXT: retq
39 %a2 = load <8 x i16>, <8 x i16>* %p2
40 %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
41 %2 = add <4 x i32> %1, %a0
42 ret <4 x i32> %2
43 }
44
45 define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_commute_load1(<4 x i32> %a0, <8 x i16>* %p1, <8 x i16> %a2) {
46 ; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_commute_load1:
47 ; CHECK: # %bb.0:
48 ; CHECK-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
49 ; CHECK-NEXT: retq
50 %a1 = load <8 x i16>, <8 x i16>* %p1
51 %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
52 %2 = add <4 x i32> %a0, %1
53 ret <4 x i32> %2
54 }
55
56 define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_commute_load2(<4 x i32> %a0, <8 x i16> %a1, <8 x i16>* %p2) {
57 ; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_commute_load2:
58 ; CHECK: # %bb.0:
59 ; CHECK-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
60 ; CHECK-NEXT: retq
61 %a2 = load <8 x i16>, <8 x i16>* %p2
62 %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
63 %2 = add <4 x i32> %a0, %1
64 ret <4 x i32> %2
65 }
66
67 define <8 x i32> @test_pmaddwd_v16i16_add_v8i32(<8 x i32> %a0, <16 x i16> %a1, <16 x i16> %a2) {
68 ; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32:
69 ; CHECK: # %bb.0:
70 ; CHECK-NEXT: vpdpwssd %ymm2, %ymm1, %ymm0
71 ; CHECK-NEXT: retq
72 %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
73 %2 = add <8 x i32> %1, %a0
74 ret <8 x i32> %2
75 }
76
77 define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_commute(<8 x i32> %a0, <16 x i16> %a1, <16 x i16> %a2) {
78 ; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_commute:
79 ; CHECK: # %bb.0:
80 ; CHECK-NEXT: vpdpwssd %ymm2, %ymm1, %ymm0
81 ; CHECK-NEXT: retq
82 %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
83 %2 = add <8 x i32> %a0, %1
84 ret <8 x i32> %2
85 }
86
87 define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_load1(<8 x i32> %a0, <16 x i16>* %p1, <16 x i16> %a2) {
88 ; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_load1:
89 ; CHECK: # %bb.0:
90 ; CHECK-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
91 ; CHECK-NEXT: retq
92 %a1 = load <16 x i16>, <16 x i16>* %p1
93 %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
94 %2 = add <8 x i32> %1, %a0
95 ret <8 x i32> %2
96 }
97
98 define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_load2(<8 x i32> %a0, <16 x i16> %a1, <16 x i16>* %p2) {
99 ; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_load2:
100 ; CHECK: # %bb.0:
101 ; CHECK-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
102 ; CHECK-NEXT: retq
103 %a2 = load <16 x i16>, <16 x i16>* %p2
104 %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
105 %2 = add <8 x i32> %1, %a0
106 ret <8 x i32> %2
107 }
108
109 define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_commute_load1(<8 x i32> %a0, <16 x i16>* %p1, <16 x i16> %a2) {
110 ; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_commute_load1:
111 ; CHECK: # %bb.0:
112 ; CHECK-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
113 ; CHECK-NEXT: retq
114 %a1 = load <16 x i16>, <16 x i16>* %p1
115 %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
116 %2 = add <8 x i32> %a0, %1
117 ret <8 x i32> %2
118 }
119
120 define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_commute_load2(<8 x i32> %a0, <16 x i16> %a1, <16 x i16>* %p2) {
121 ; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_commute_load2:
122 ; CHECK: # %bb.0:
123 ; CHECK-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
124 ; CHECK-NEXT: retq
125 %a2 = load <16 x i16>, <16 x i16>* %p2
126 %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
127 %2 = add <8 x i32> %a0, %1
128 ret <8 x i32> %2
129 }
130
131 define <16 x i32> @test_pmaddwd_v32i16_add_v16i32(<16 x i32> %a0, <32 x i16> %a1, <32 x i16> %a2) {
132 ; CHECK-LABEL: test_pmaddwd_v32i16_add_v16i32:
133 ; CHECK: # %bb.0:
134 ; CHECK-NEXT: vpdpwssd %zmm2, %zmm1, %zmm0
135 ; CHECK-NEXT: retq
136 %1 = call <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16> %a1, <32 x i16> %a2)
137 %2 = add <16 x i32> %1, %a0
138 ret <16 x i32> %2
139 }
140
141 define <16 x i32> @test_pmaddwd_v32i16_add_v16i32_commute(<16 x i32> %a0, <32 x i16> %a1, <32 x i16> %a2) {
142 ; CHECK-LABEL: test_pmaddwd_v32i16_add_v16i32_commute:
143 ; CHECK: # %bb.0:
144 ; CHECK-NEXT: vpdpwssd %zmm2, %zmm1, %zmm0
145 ; CHECK-NEXT: retq
146 %1 = call <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16> %a1, <32 x i16> %a2)
147 %2 = add <16 x i32> %a0, %1
148 ret <16 x i32> %2
149 }
150
151 define <16 x i32> @test_pmaddwd_v32i16_add_v16i32_load1(<16 x i32> %a0, <32 x i16>* %p1, <32 x i16> %a2) {
152 ; CHECK-LABEL: test_pmaddwd_v32i16_add_v16i32_load1:
153 ; CHECK: # %bb.0:
154 ; CHECK-NEXT: vpdpwssd (%rdi), %zmm1, %zmm0
155 ; CHECK-NEXT: retq
156 %a1 = load <32 x i16>, <32 x i16>* %p1
157 %1 = call <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16> %a1, <32 x i16> %a2)
158 %2 = add <16 x i32> %1, %a0
159 ret <16 x i32> %2
160 }
161
162 define <16 x i32> @test_pmaddwd_v32i16_add_v16i32_load2(<16 x i32> %a0, <32 x i16> %a1, <32 x i16>* %p2) {
163 ; CHECK-LABEL: test_pmaddwd_v32i16_add_v16i32_load2:
164 ; CHECK: # %bb.0:
165 ; CHECK-NEXT: vpdpwssd (%rdi), %zmm1, %zmm0
166 ; CHECK-NEXT: retq
167 %a2 = load <32 x i16>, <32 x i16>* %p2
168 %1 = call <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16> %a1, <32 x i16> %a2)
169 %2 = add <16 x i32> %1, %a0
170 ret <16 x i32> %2
171 }
172
173 define <16 x i32> @test_pmaddwd_v32i16_add_v16i32_commute_load1(<16 x i32> %a0, <32 x i16>* %p1, <32 x i16> %a2) {
174 ; CHECK-LABEL: test_pmaddwd_v32i16_add_v16i32_commute_load1:
175 ; CHECK: # %bb.0:
176 ; CHECK-NEXT: vpdpwssd (%rdi), %zmm1, %zmm0
177 ; CHECK-NEXT: retq
178 %a1 = load <32 x i16>, <32 x i16>* %p1
179 %1 = call <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16> %a1, <32 x i16> %a2)
180 %2 = add <16 x i32> %a0, %1
181 ret <16 x i32> %2
182 }
183
184 define <16 x i32> @test_pmaddwd_v32i16_add_v16i32_commute_load2(<16 x i32> %a0, <32 x i16> %a1, <32 x i16>* %p2) {
185 ; CHECK-LABEL: test_pmaddwd_v32i16_add_v16i32_commute_load2:
186 ; CHECK: # %bb.0:
187 ; CHECK-NEXT: vpdpwssd (%rdi), %zmm1, %zmm0
188 ; CHECK-NEXT: retq
189 %a2 = load <32 x i16>, <32 x i16>* %p2
190 %1 = call <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16> %a1, <32 x i16> %a2)
191 %2 = add <16 x i32> %a0, %1
192 ret <16 x i32> %2
193 }
194
195 declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>)
196 declare <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16>, <16 x i16>)
197 declare <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16>, <32 x i16>)