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[AMDGPU] gfx1010 SOP instructions Differential Revision: https://reviews.llvm.org/D61080 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359139 91177308-0d34-0410-b5e6-96231b3b80d8 Stanislav Mekhanoshin 1 year, 5 months ago
8 changed file(s) with 560 addition(s) and 165 deletion(s). Raw diff Collapse all Expand all
245245 def S_MOVRELD_B64 : SOP1_64 <"s_movreld_b64">;
246246 } // End Uses = [M0]
247247
248 let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in {
248249 def S_CBRANCH_JOIN : SOP1_0_32R <"s_cbranch_join">;
249250 def S_MOV_REGRD_B32 : SOP1_32 <"s_mov_regrd_b32">;
251 } // End SubtargetPredicate = isGFX6GFX7GFX8GFX9
250252
251253 let Defs = [SCC] in {
252254 def S_ABS_I32 : SOP1_32 <"s_abs_i32">;
271273 def S_BITREPLICATE_B64_B32 : SOP1_64_32<"s_bitreplicate_b64_b32">;
272274 } // End SubtargetPredicate = isGFX9Plus
273275
276 let SubtargetPredicate = isGFX10Plus in {
277 let Uses = [M0] in {
278 def S_MOVRELSD_2_B32 : SOP1_32<"s_movrelsd_2_b32">;
279 } // End Uses = [M0]
280 } // End SubtargetPredicate = isGFX10Plus
281
274282 //===----------------------------------------------------------------------===//
275283 // SOP2 Instructions
276284 //===----------------------------------------------------------------------===//
519527 "$src0, $src1"
520528 > {
521529 let has_sdst = 0;
530 let SubtargetPredicate = isGFX6GFX7GFX8GFX9;
522531 }
523532
524533 let Defs = [SCC] in {
628637 "$sdst, $simm16",
629638 pattern>;
630639
640 class SOPK_32_BR pattern=[]> : SOPK_Pseudo <
641 opName,
642 (outs),
643 (ins sopp_brtarget:$simm16, SReg_32:$sdst),
644 "$sdst, $simm16",
645 pattern> {
646 let Defs = [EXEC];
647 let Uses = [EXEC];
648 let isBranch = 1;
649 let isTerminator = 1;
650 let SchedRW = [WriteBranch];
651 }
652
631653 class SOPK_SCC : SOPK_Pseudo <
632654 opName,
633655 (outs),
694716 def S_MULK_I32 : SOPK_32TIE <"s_mulk_i32">;
695717 }
696718
719 let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in
697720 def S_CBRANCH_I_FORK : SOPK_Pseudo <
698721 "s_cbranch_i_fork",
699722 (outs), (ins SReg_64:$sdst, s16imm:$simm16),
729752 }
730753
731754 } // End hasSideEffects = 1
755
756 class SOPK_WAITCNT pat=[]> :
757 SOPK_Pseudo<
758 opName,
759 (outs),
760 (ins SReg_32:$sdst, s16imm:$simm16),
761 "$sdst, $simm16",
762 pat> {
763 let hasSideEffects = 1;
764 let mayLoad = 1;
765 let mayStore = 1;
766 let has_sdst = 1; // First source takes place of sdst in encoding
767 }
732768
733769 let SubtargetPredicate = isGFX9Plus in {
734770 def S_CALL_B64 : SOPK_Pseudo<
739775 let isCall = 1;
740776 }
741777 } // End SubtargetPredicate = isGFX9Plus
778
779 let SubtargetPredicate = isGFX10Plus in {
780 def S_VERSION : SOPK_Pseudo<
781 "s_version",
782 (outs),
783 (ins s16imm:$simm16),
784 "$simm16"> {
785 let has_sdst = 0;
786 }
787
788 def S_WAITCNT_VSCNT : SOPK_WAITCNT<"s_waitcnt_vscnt">;
789 def S_WAITCNT_VMCNT : SOPK_WAITCNT<"s_waitcnt_vmcnt">;
790 def S_WAITCNT_EXPCNT : SOPK_WAITCNT<"s_waitcnt_expcnt">;
791 def S_WAITCNT_LGKMCNT : SOPK_WAITCNT<"s_waitcnt_lgkmcnt">;
792 } // End SubtargetPredicate = isGFX10Plus
742793
743794 //===----------------------------------------------------------------------===//
744795 // SOPC Instructions
820871 def S_BITCMP1_B32 : SOPC_32 <0x0d, "s_bitcmp1_b32">;
821872 def S_BITCMP0_B64 : SOPC_64_32 <0x0e, "s_bitcmp0_b64">;
822873 def S_BITCMP1_B64 : SOPC_64_32 <0x0f, "s_bitcmp1_b64">;
874 let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in
823875 def S_SETVSKIP : SOPC_32 <0x10, "s_setvskip">;
824876
825877 let SubtargetPredicate = isGFX8Plus in {
889941 } // End isBarrier = 1, isReturn = 1, simm16 = 0
890942 } // End SubtargetPredicate = isGFX9Plus
891943
944 let SubtargetPredicate = isGFX10Plus in {
945 let isBarrier = 1, isReturn = 1, simm16 = 0 in {
946 def S_CODE_END :
947 SOPP<0x01f, (ins), "s_code_end">;
948 } // End isBarrier = 1, isReturn = 1, simm16 = 0
949 } // End SubtargetPredicate = isGFX10Plus
950
892951 let isBranch = 1, SchedRW = [WriteBranch] in {
893952 def S_BRANCH : SOPP <
894953 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",
10321091 }
10331092 }
10341093
1094 let SubtargetPredicate = isGFX10Plus in {
1095 def S_INST_PREFETCH :
1096 SOPP<0x020, (ins s16imm:$simm16), "s_inst_prefetch $simm16">;
1097 def S_CLAUSE :
1098 SOPP<0x021, (ins s16imm:$simm16), "s_clause $simm16">;
1099 def S_WAITCNT_IDLE :
1100 SOPP <0x022, (ins), "s_wait_idle"> {
1101 let simm16 = 0;
1102 }
1103 def S_WAITCNT_DEPCTR :
1104 SOPP <0x023, (ins s16imm:$simm16), "s_waitcnt_depctr $simm16">;
1105 def S_ROUND_MODE :
1106 SOPP<0x024, (ins s16imm:$simm16), "s_round_mode $simm16">;
1107 def S_DENORM_MODE :
1108 SOPP<0x025, (ins s16imm:$simm16), "s_denorm_mode $simm16">;
1109 def S_TTRACEDATA_IMM :
1110 SOPP<0x028, (ins s16imm:$simm16), "s_ttracedata_imm $simm16">;
1111 } // End SubtargetPredicate = isGFX10Plus
1112
10351113 //===----------------------------------------------------------------------===//
10361114 // S_GETREG_B32 Intrinsic Pattern.
10371115 //===----------------------------------------------------------------------===//
11211199 // Target-specific instruction encodings.
11221200 //===----------------------------------------------------------------------===//
11231201
1124 class Select_si :
1125 SIMCInstr {
1126 list AssemblerPredicates = [isGFX6GFX7];
1127 string DecoderNamespace = "GFX6GFX7";
1128 }
1129
1130 class SOP1_Real_si op, SOP1_Pseudo ps> :
1131 SOP1_Real,
1132 Select_si;
1133
1134 class SOP2_Real_si op, SOP2_Pseudo ps> :
1135 SOP2_Real,
1136 Select_si;
1137
1138 class SOPK_Real_si op, SOPK_Pseudo ps> :
1139 SOPK_Real32,
1140 Select_si;
1141
1142 def S_MOV_B32_si : SOP1_Real_si <0x03, S_MOV_B32>;
1143 def S_MOV_B64_si : SOP1_Real_si <0x04, S_MOV_B64>;
1144 def S_CMOV_B32_si : SOP1_Real_si <0x05, S_CMOV_B32>;
1145 def S_CMOV_B64_si : SOP1_Real_si <0x06, S_CMOV_B64>;
1146 def S_NOT_B32_si : SOP1_Real_si <0x07, S_NOT_B32>;
1147 def S_NOT_B64_si : SOP1_Real_si <0x08, S_NOT_B64>;
1148 def S_WQM_B32_si : SOP1_Real_si <0x09, S_WQM_B32>;
1149 def S_WQM_B64_si : SOP1_Real_si <0x0a, S_WQM_B64>;
1150 def S_BREV_B32_si : SOP1_Real_si <0x0b, S_BREV_B32>;
1151 def S_BREV_B64_si : SOP1_Real_si <0x0c, S_BREV_B64>;
1152 def S_BCNT0_I32_B32_si : SOP1_Real_si <0x0d, S_BCNT0_I32_B32>;
1153 def S_BCNT0_I32_B64_si : SOP1_Real_si <0x0e, S_BCNT0_I32_B64>;
1154 def S_BCNT1_I32_B32_si : SOP1_Real_si <0x0f, S_BCNT1_I32_B32>;
1155 def S_BCNT1_I32_B64_si : SOP1_Real_si <0x10, S_BCNT1_I32_B64>;
1156 def S_FF0_I32_B32_si : SOP1_Real_si <0x11, S_FF0_I32_B32>;
1157 def S_FF0_I32_B64_si : SOP1_Real_si <0x12, S_FF0_I32_B64>;
1158 def S_FF1_I32_B32_si : SOP1_Real_si <0x13, S_FF1_I32_B32>;
1159 def S_FF1_I32_B64_si : SOP1_Real_si <0x14, S_FF1_I32_B64>;
1160 def S_FLBIT_I32_B32_si : SOP1_Real_si <0x15, S_FLBIT_I32_B32>;
1161 def S_FLBIT_I32_B64_si : SOP1_Real_si <0x16, S_FLBIT_I32_B64>;
1162 def S_FLBIT_I32_si : SOP1_Real_si <0x17, S_FLBIT_I32>;
1163 def S_FLBIT_I32_I64_si : SOP1_Real_si <0x18, S_FLBIT_I32_I64>;
1164 def S_SEXT_I32_I8_si : SOP1_Real_si <0x19, S_SEXT_I32_I8>;
1165 def S_SEXT_I32_I16_si : SOP1_Real_si <0x1a, S_SEXT_I32_I16>;
1166 def S_BITSET0_B32_si : SOP1_Real_si <0x1b, S_BITSET0_B32>;
1167 def S_BITSET0_B64_si : SOP1_Real_si <0x1c, S_BITSET0_B64>;
1168 def S_BITSET1_B32_si : SOP1_Real_si <0x1d, S_BITSET1_B32>;
1169 def S_BITSET1_B64_si : SOP1_Real_si <0x1e, S_BITSET1_B64>;
1170 def S_GETPC_B64_si : SOP1_Real_si <0x1f, S_GETPC_B64>;
1171 def S_SETPC_B64_si : SOP1_Real_si <0x20, S_SETPC_B64>;
1172 def S_SWAPPC_B64_si : SOP1_Real_si <0x21, S_SWAPPC_B64>;
1173 def S_RFE_B64_si : SOP1_Real_si <0x22, S_RFE_B64>;
1174 def S_AND_SAVEEXEC_B64_si : SOP1_Real_si <0x24, S_AND_SAVEEXEC_B64>;
1175 def S_OR_SAVEEXEC_B64_si : SOP1_Real_si <0x25, S_OR_SAVEEXEC_B64>;
1176 def S_XOR_SAVEEXEC_B64_si : SOP1_Real_si <0x26, S_XOR_SAVEEXEC_B64>;
1177 def S_ANDN2_SAVEEXEC_B64_si: SOP1_Real_si <0x27, S_ANDN2_SAVEEXEC_B64>;
1178 def S_ORN2_SAVEEXEC_B64_si : SOP1_Real_si <0x28, S_ORN2_SAVEEXEC_B64>;
1179 def S_NAND_SAVEEXEC_B64_si : SOP1_Real_si <0x29, S_NAND_SAVEEXEC_B64>;
1180 def S_NOR_SAVEEXEC_B64_si : SOP1_Real_si <0x2a, S_NOR_SAVEEXEC_B64>;
1181 def S_XNOR_SAVEEXEC_B64_si : SOP1_Real_si <0x2b, S_XNOR_SAVEEXEC_B64>;
1182 def S_QUADMASK_B32_si : SOP1_Real_si <0x2c, S_QUADMASK_B32>;
1183 def S_QUADMASK_B64_si : SOP1_Real_si <0x2d, S_QUADMASK_B64>;
1184 def S_MOVRELS_B32_si : SOP1_Real_si <0x2e, S_MOVRELS_B32>;
1185 def S_MOVRELS_B64_si : SOP1_Real_si <0x2f, S_MOVRELS_B64>;
1186 def S_MOVRELD_B32_si : SOP1_Real_si <0x30, S_MOVRELD_B32>;
1187 def S_MOVRELD_B64_si : SOP1_Real_si <0x31, S_MOVRELD_B64>;
1188 def S_CBRANCH_JOIN_si : SOP1_Real_si <0x32, S_CBRANCH_JOIN>;
1189 def S_MOV_REGRD_B32_si : SOP1_Real_si <0x33, S_MOV_REGRD_B32>;
1190 def S_ABS_I32_si : SOP1_Real_si <0x34, S_ABS_I32>;
1191 def S_MOV_FED_B32_si : SOP1_Real_si <0x35, S_MOV_FED_B32>;
1192
1193 def S_ADD_U32_si : SOP2_Real_si <0x00, S_ADD_U32>;
1194 def S_ADD_I32_si : SOP2_Real_si <0x02, S_ADD_I32>;
1195 def S_SUB_U32_si : SOP2_Real_si <0x01, S_SUB_U32>;
1196 def S_SUB_I32_si : SOP2_Real_si <0x03, S_SUB_I32>;
1197 def S_ADDC_U32_si : SOP2_Real_si <0x04, S_ADDC_U32>;
1198 def S_SUBB_U32_si : SOP2_Real_si <0x05, S_SUBB_U32>;
1199 def S_MIN_I32_si : SOP2_Real_si <0x06, S_MIN_I32>;
1200 def S_MIN_U32_si : SOP2_Real_si <0x07, S_MIN_U32>;
1201 def S_MAX_I32_si : SOP2_Real_si <0x08, S_MAX_I32>;
1202 def S_MAX_U32_si : SOP2_Real_si <0x09, S_MAX_U32>;
1203 def S_CSELECT_B32_si : SOP2_Real_si <0x0a, S_CSELECT_B32>;
1204 def S_CSELECT_B64_si : SOP2_Real_si <0x0b, S_CSELECT_B64>;
1205 def S_AND_B32_si : SOP2_Real_si <0x0e, S_AND_B32>;
1206 def S_AND_B64_si : SOP2_Real_si <0x0f, S_AND_B64>;
1207 def S_OR_B32_si : SOP2_Real_si <0x10, S_OR_B32>;
1208 def S_OR_B64_si : SOP2_Real_si <0x11, S_OR_B64>;
1209 def S_XOR_B32_si : SOP2_Real_si <0x12, S_XOR_B32>;
1210 def S_XOR_B64_si : SOP2_Real_si <0x13, S_XOR_B64>;
1211 def S_ANDN2_B32_si : SOP2_Real_si <0x14, S_ANDN2_B32>;
1212 def S_ANDN2_B64_si : SOP2_Real_si <0x15, S_ANDN2_B64>;
1213 def S_ORN2_B32_si : SOP2_Real_si <0x16, S_ORN2_B32>;
1214 def S_ORN2_B64_si : SOP2_Real_si <0x17, S_ORN2_B64>;
1215 def S_NAND_B32_si : SOP2_Real_si <0x18, S_NAND_B32>;
1216 def S_NAND_B64_si : SOP2_Real_si <0x19, S_NAND_B64>;
1217 def S_NOR_B32_si : SOP2_Real_si <0x1a, S_NOR_B32>;
1218 def S_NOR_B64_si : SOP2_Real_si <0x1b, S_NOR_B64>;
1219 def S_XNOR_B32_si : SOP2_Real_si <0x1c, S_XNOR_B32>;
1220 def S_XNOR_B64_si : SOP2_Real_si <0x1d, S_XNOR_B64>;
1221 def S_LSHL_B32_si : SOP2_Real_si <0x1e, S_LSHL_B32>;
1222 def S_LSHL_B64_si : SOP2_Real_si <0x1f, S_LSHL_B64>;
1223 def S_LSHR_B32_si : SOP2_Real_si <0x20, S_LSHR_B32>;
1224 def S_LSHR_B64_si : SOP2_Real_si <0x21, S_LSHR_B64>;
1225 def S_ASHR_I32_si : SOP2_Real_si <0x22, S_ASHR_I32>;
1226 def S_ASHR_I64_si : SOP2_Real_si <0x23, S_ASHR_I64>;
1227 def S_BFM_B32_si : SOP2_Real_si <0x24, S_BFM_B32>;
1228 def S_BFM_B64_si : SOP2_Real_si <0x25, S_BFM_B64>;
1229 def S_MUL_I32_si : SOP2_Real_si <0x26, S_MUL_I32>;
1230 def S_BFE_U32_si : SOP2_Real_si <0x27, S_BFE_U32>;
1231 def S_BFE_I32_si : SOP2_Real_si <0x28, S_BFE_I32>;
1232 def S_BFE_U64_si : SOP2_Real_si <0x29, S_BFE_U64>;
1233 def S_BFE_I64_si : SOP2_Real_si <0x2a, S_BFE_I64>;
1234 def S_CBRANCH_G_FORK_si : SOP2_Real_si <0x2b, S_CBRANCH_G_FORK>;
1235 def S_ABSDIFF_I32_si : SOP2_Real_si <0x2c, S_ABSDIFF_I32>;
1236
1237 def S_MOVK_I32_si : SOPK_Real_si <0x00, S_MOVK_I32>;
1238 def S_CMOVK_I32_si : SOPK_Real_si <0x02, S_CMOVK_I32>;
1239 def S_CMPK_EQ_I32_si : SOPK_Real_si <0x03, S_CMPK_EQ_I32>;
1240 def S_CMPK_LG_I32_si : SOPK_Real_si <0x04, S_CMPK_LG_I32>;
1241 def S_CMPK_GT_I32_si : SOPK_Real_si <0x05, S_CMPK_GT_I32>;
1242 def S_CMPK_GE_I32_si : SOPK_Real_si <0x06, S_CMPK_GE_I32>;
1243 def S_CMPK_LT_I32_si : SOPK_Real_si <0x07, S_CMPK_LT_I32>;
1244 def S_CMPK_LE_I32_si : SOPK_Real_si <0x08, S_CMPK_LE_I32>;
1245 def S_CMPK_EQ_U32_si : SOPK_Real_si <0x09, S_CMPK_EQ_U32>;
1246 def S_CMPK_LG_U32_si : SOPK_Real_si <0x0a, S_CMPK_LG_U32>;
1247 def S_CMPK_GT_U32_si : SOPK_Real_si <0x0b, S_CMPK_GT_U32>;
1248 def S_CMPK_GE_U32_si : SOPK_Real_si <0x0c, S_CMPK_GE_U32>;
1249 def S_CMPK_LT_U32_si : SOPK_Real_si <0x0d, S_CMPK_LT_U32>;
1250 def S_CMPK_LE_U32_si : SOPK_Real_si <0x0e, S_CMPK_LE_U32>;
1251 def S_ADDK_I32_si : SOPK_Real_si <0x0f, S_ADDK_I32>;
1252 def S_MULK_I32_si : SOPK_Real_si <0x10, S_MULK_I32>;
1253 def S_CBRANCH_I_FORK_si : SOPK_Real_si <0x11, S_CBRANCH_I_FORK>;
1254 def S_GETREG_B32_si : SOPK_Real_si <0x12, S_GETREG_B32>;
1255 def S_SETREG_B32_si : SOPK_Real_si <0x13, S_SETREG_B32>;
1256 //def S_GETREG_REGRD_B32_si : SOPK_Real_si <0x14, S_GETREG_REGRD_B32>; // see pseudo for comments
1257 def S_SETREG_IMM32_B32_si : SOPK_Real64<0x15, S_SETREG_IMM32_B32>,
1258 Select_si;
1259
1202 //===----------------------------------------------------------------------===//
1203 // SOP1 - GFX10.
1204 //===----------------------------------------------------------------------===//
1205
1206 class Select_gfx10 : SIMCInstr {
1207 Predicate AssemblerPredicate = isGFX10Plus;
1208 string DecoderNamespace = "GFX10";
1209 }
1210
1211 multiclass SOP1_Real_gfx10 op> {
1212 def _gfx10 : SOP1_Real(NAME)>,
1213 Select_gfx10(NAME).Mnemonic>;
1214 }
1215
1216 defm S_ANDN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x037>;
1217 defm S_ORN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x038>;
1218 defm S_ANDN1_WREXEC_B64 : SOP1_Real_gfx10<0x039>;
1219 defm S_ANDN2_WREXEC_B64 : SOP1_Real_gfx10<0x03a>;
1220 defm S_BITREPLICATE_B64_B32 : SOP1_Real_gfx10<0x03b>;
1221 defm S_MOVRELSD_2_B32 : SOP1_Real_gfx10<0x049>;
1222
1223 //===----------------------------------------------------------------------===//
1224 // SOP1 - GFX6, GFX7.
1225 //===----------------------------------------------------------------------===//
1226
1227 class Select_gfx6_gfx7 : SIMCInstr {
1228 Predicate AssemblerPredicate = isGFX6GFX7;
1229 string DecoderNamespace = "GFX6GFX7";
1230 }
1231
1232 multiclass SOP1_Real_gfx6_gfx7 op> {
1233 def _gfx6_gfx7 : SOP1_Real(NAME)>,
1234 Select_gfx6_gfx7(NAME).Mnemonic>;
1235 }
1236
1237 multiclass SOP1_Real_gfx6_gfx7_gfx10 op> :
1238 SOP1_Real_gfx6_gfx7, SOP1_Real_gfx10;
1239
1240 defm S_CBRANCH_JOIN : SOP1_Real_gfx6_gfx7<0x032>;
1241 defm S_MOV_REGRD_B32 : SOP1_Real_gfx6_gfx7<0x033>;
1242
1243 defm S_MOV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x003>;
1244 defm S_MOV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x004>;
1245 defm S_CMOV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x005>;
1246 defm S_CMOV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x006>;
1247 defm S_NOT_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x007>;
1248 defm S_NOT_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x008>;
1249 defm S_WQM_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x009>;
1250 defm S_WQM_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00a>;
1251 defm S_BREV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00b>;
1252 defm S_BREV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00c>;
1253 defm S_BCNT0_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00d>;
1254 defm S_BCNT0_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00e>;
1255 defm S_BCNT1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00f>;
1256 defm S_BCNT1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x010>;
1257 defm S_FF0_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x011>;
1258 defm S_FF0_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x012>;
1259 defm S_FF1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x013>;
1260 defm S_FF1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x014>;
1261 defm S_FLBIT_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x015>;
1262 defm S_FLBIT_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x016>;
1263 defm S_FLBIT_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x017>;
1264 defm S_FLBIT_I32_I64 : SOP1_Real_gfx6_gfx7_gfx10<0x018>;
1265 defm S_SEXT_I32_I8 : SOP1_Real_gfx6_gfx7_gfx10<0x019>;
1266 defm S_SEXT_I32_I16 : SOP1_Real_gfx6_gfx7_gfx10<0x01a>;
1267 defm S_BITSET0_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x01b>;
1268 defm S_BITSET0_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01c>;
1269 defm S_BITSET1_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x01d>;
1270 defm S_BITSET1_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01e>;
1271 defm S_GETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01f>;
1272 defm S_SETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x020>;
1273 defm S_SWAPPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x021>;
1274 defm S_RFE_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x022>;
1275 defm S_AND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x024>;
1276 defm S_OR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x025>;
1277 defm S_XOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x026>;
1278 defm S_ANDN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x027>;
1279 defm S_ORN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x028>;
1280 defm S_NAND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x029>;
1281 defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02a>;
1282 defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02b>;
1283 defm S_QUADMASK_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02c>;
1284 defm S_QUADMASK_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02d>;
1285 defm S_MOVRELS_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02e>;
1286 defm S_MOVRELS_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02f>;
1287 defm S_MOVRELD_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x030>;
1288 defm S_MOVRELD_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x031>;
1289 defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>;
1290 defm S_MOV_FED_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x035>;
1291
1292 //===----------------------------------------------------------------------===//
1293 // SOP2 - GFX10.
1294 //===----------------------------------------------------------------------===//
1295
1296 multiclass SOP2_Real_gfx10 op> {
1297 def _gfx10 : SOP2_Real(NAME)>,
1298 Select_gfx10(NAME).Mnemonic>;
1299 }
1300
1301 defm S_LSHL1_ADD_U32 : SOP2_Real_gfx10<0x02e>;
1302 defm S_LSHL2_ADD_U32 : SOP2_Real_gfx10<0x02f>;
1303 defm S_LSHL3_ADD_U32 : SOP2_Real_gfx10<0x030>;
1304 defm S_LSHL4_ADD_U32 : SOP2_Real_gfx10<0x031>;
1305 defm S_PACK_LL_B32_B16 : SOP2_Real_gfx10<0x032>;
1306 defm S_PACK_LH_B32_B16 : SOP2_Real_gfx10<0x033>;
1307 defm S_PACK_HH_B32_B16 : SOP2_Real_gfx10<0x034>;
1308 defm S_MUL_HI_U32 : SOP2_Real_gfx10<0x035>;
1309 defm S_MUL_HI_I32 : SOP2_Real_gfx10<0x036>;
1310
1311 //===----------------------------------------------------------------------===//
1312 // SOP2 - GFX6, GFX7.
1313 //===----------------------------------------------------------------------===//
1314
1315 multiclass SOP2_Real_gfx6_gfx7 op> {
1316 def _gfx6_gfx7 : SOP2_Real(NAME)>,
1317 Select_gfx6_gfx7(NAME).Mnemonic>;
1318 }
1319
1320 multiclass SOP2_Real_gfx6_gfx7_gfx10 op> :
1321 SOP2_Real_gfx6_gfx7, SOP2_Real_gfx10;
1322
1323 defm S_CBRANCH_G_FORK : SOP2_Real_gfx6_gfx7<0x02b>;
1324
1325 defm S_ADD_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x000>;
1326 defm S_SUB_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x001>;
1327 defm S_ADD_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x002>;
1328 defm S_SUB_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x003>;
1329 defm S_ADDC_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x004>;
1330 defm S_SUBB_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x005>;
1331 defm S_MIN_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x006>;
1332 defm S_MIN_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x007>;
1333 defm S_MAX_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x008>;
1334 defm S_MAX_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x009>;
1335 defm S_CSELECT_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x00a>;
1336 defm S_CSELECT_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x00b>;
1337 defm S_AND_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x00e>;
1338 defm S_AND_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x00f>;
1339 defm S_OR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x010>;
1340 defm S_OR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x011>;
1341 defm S_XOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x012>;
1342 defm S_XOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x013>;
1343 defm S_ANDN2_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x014>;
1344 defm S_ANDN2_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x015>;
1345 defm S_ORN2_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x016>;
1346 defm S_ORN2_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x017>;
1347 defm S_NAND_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x018>;
1348 defm S_NAND_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x019>;
1349 defm S_NOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01a>;
1350 defm S_NOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01b>;
1351 defm S_XNOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01c>;
1352 defm S_XNOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01d>;
1353 defm S_LSHL_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01e>;
1354 defm S_LSHL_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01f>;
1355 defm S_LSHR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x020>;
1356 defm S_LSHR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x021>;
1357 defm S_ASHR_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x022>;
1358 defm S_ASHR_I64 : SOP2_Real_gfx6_gfx7_gfx10<0x023>;
1359 defm S_BFM_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x024>;
1360 defm S_BFM_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x025>;
1361 defm S_MUL_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x026>;
1362 defm S_BFE_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x027>;
1363 defm S_BFE_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x028>;
1364 defm S_BFE_U64 : SOP2_Real_gfx6_gfx7_gfx10<0x029>;
1365 defm S_BFE_I64 : SOP2_Real_gfx6_gfx7_gfx10<0x02a>;
1366 defm S_ABSDIFF_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x02c>;
1367
1368 //===----------------------------------------------------------------------===//
1369 // SOPK - GFX10.
1370 //===----------------------------------------------------------------------===//
1371
1372 multiclass SOPK_Real32_gfx10 op> {
1373 def _gfx10 : SOPK_Real32(NAME)>,
1374 Select_gfx10(NAME).Mnemonic>;
1375 }
1376
1377 multiclass SOPK_Real64_gfx10 op> {
1378 def _gfx10 : SOPK_Real64(NAME)>,
1379 Select_gfx10(NAME).Mnemonic>;
1380 }
1381
1382 defm S_VERSION : SOPK_Real32_gfx10<0x001>;
1383 defm S_CALL_B64 : SOPK_Real32_gfx10<0x016>;
1384 defm S_WAITCNT_VSCNT : SOPK_Real32_gfx10<0x017>;
1385 defm S_WAITCNT_VMCNT : SOPK_Real32_gfx10<0x018>;
1386 defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx10<0x019>;
1387 defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx10<0x01a>;
1388
1389 //===----------------------------------------------------------------------===//
1390 // SOPK - GFX6, GFX7.
1391 //===----------------------------------------------------------------------===//
1392
1393 multiclass SOPK_Real32_gfx6_gfx7 op> {
1394 def _gfx6_gfx7 : SOPK_Real32(NAME)>,
1395 Select_gfx6_gfx7(NAME).Mnemonic>;
1396 }
1397
1398 multiclass SOPK_Real64_gfx6_gfx7 op> {
1399 def _gfx6_gfx7 : SOPK_Real64(NAME)>,
1400 Select_gfx6_gfx7(NAME).Mnemonic>;
1401 }
1402
1403 multiclass SOPK_Real32_gfx6_gfx7_gfx10 op> :
1404 SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10;
1405
1406 multiclass SOPK_Real64_gfx6_gfx7_gfx10 op> :
1407 SOPK_Real64_gfx6_gfx7, SOPK_Real64_gfx10;
1408
1409 defm S_CBRANCH_I_FORK : SOPK_Real32_gfx6_gfx7<0x011>;
1410
1411 defm S_MOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x000>;
1412 defm S_CMOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x002>;
1413 defm S_CMPK_EQ_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x003>;
1414 defm S_CMPK_LG_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x004>;
1415 defm S_CMPK_GT_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x005>;
1416 defm S_CMPK_GE_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x006>;
1417 defm S_CMPK_LT_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x007>;
1418 defm S_CMPK_LE_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x008>;
1419 defm S_CMPK_EQ_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x009>;
1420 defm S_CMPK_LG_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00a>;
1421 defm S_CMPK_GT_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00b>;
1422 defm S_CMPK_GE_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00c>;
1423 defm S_CMPK_LT_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00d>;
1424 defm S_CMPK_LE_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00e>;
1425 defm S_ADDK_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00f>;
1426 defm S_MULK_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x010>;
1427 defm S_GETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x012>;
1428 defm S_SETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x013>;
1429 defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>;
1430
1431 //===----------------------------------------------------------------------===//
1432 // GFX8, GFX9 (VI).
1433 //===----------------------------------------------------------------------===//
12601434
12611435 class Select_vi :
12621436 SIMCInstr {
None // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s
1 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s
0 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,SICIVI9-ERR,SIVICI-ERR,SI-ERR %s
1 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,SICIVI9-ERR,SIVICI-ERR,CIVI9-ERR %s
2 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,GFX9-ERR,SICIVI9-ERR,CIVI9-ERR %s
3 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,GFX10-ERR %s
4
5 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=SIVICI %s
6 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=SIVICI %s
7 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX9 %s
8 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX10 %s
9
10 s_add_i32 s106, s0, s1
11 // GCN-ERR: error: not a valid operand
212
313 s_add_i32 s104, s0, s1
4 // CHECK: error: not a valid operand
14 // SICIVI9-ERR: error: not a valid operand
15 // GFX10: s_add_i32 s104, s0, s1 ; encoding:
516
617 s_add_i32 s105, s0, s1
7 // CHECK: error: not a valid operand
18 // SICIVI9-ERR: error: not a valid operand
19 // GFX10: s_add_i32 s105, s0, s1 ; encoding:
820
921 v_add_i32 v256, v0, v1
10 // CHECK: error: not a valid operand
22 // GCN-ERR: error: not a valid operand
1123
1224 v_add_i32 v257, v0, v1
13 // CHECK: error: not a valid operand
25 // GCN-ERR: error: not a valid operand
1426
1527 s_mov_b64 s[0:17], -1
16 // CHECK: error: not a valid operand
28 // GCN-ERR: error: not a valid operand
1729
1830 s_mov_b64 s[103:104], -1
19 // CHECK: error: not a valid operand
31 // GCN-ERR: error: not a valid operand
32
33 s_mov_b64 s[105:106], -1
34 // GCN-ERR: error: not a valid operand
2035
2136 s_mov_b64 s[104:105], -1
22 // CHECK: error: not a valid operand
37 // SICIVI9-ERR: error: not a valid operand
38 // GFX10: s_mov_b64 s[104:105], -1 ; encoding:
2339
2440 s_load_dwordx4 s[102:105], s[2:3], s4
25 // CHECK: error: not a valid operand
41 // GCN-ERR: error: not a valid operand
2642
2743 s_load_dwordx4 s[104:108], s[2:3], s4
28 // CHECK: error: not a valid operand
44 // GCN-ERR: error: not a valid operand
2945
3046 s_load_dwordx4 s[108:112], s[2:3], s4
31 // CHECK: error: not a valid operand
47 // GCN-ERR: error: not a valid operand
3248
3349 s_load_dwordx4 s[1:4], s[2:3], s4
34 // CHECK: error: not a valid operand
50 // GCN-ERR: error: not a valid operand
3551
3652 s_load_dwordx4 s[1:4], s[2:3], s4
37 // CHECK: error: not a valid operand
53 // GCN-ERR: error: not a valid operand
3854
3955 s_load_dwordx8 s[104:111], s[2:3], s4
40 // CHECK: error: not a valid operand
56 // GCN-ERR: error: not a valid operand
4157
4258 s_load_dwordx8 s[100:107], s[2:3], s4
43 // CHECK: error: not a valid operand
59 // GCN-ERR: error: not a valid operand
4460
4561 s_load_dwordx8 s[108:115], s[2:3], s4
46 // CHECK: error: not a valid operand
62 // GCN-ERR: error: not a valid operand
4763
4864 s_load_dwordx16 s[92:107], s[2:3], s4
49 // CHECK: error: not a valid operand
65 // GCN-ERR: error: not a valid operand
5066
5167 s_load_dwordx16 s[96:111], s[2:3], s4
52 // CHECK: error: not a valid operand
68 // GCN-ERR: error: not a valid operand
5369
5470 s_load_dwordx16 s[100:115], s[2:3], s4
55 // CHECK: error: not a valid operand
71 // GCN-ERR: error: not a valid operand
5672
5773 s_load_dwordx16 s[104:119], s[2:3], s4
58 // CHECK: error: not a valid operand
74 // GCN-ERR: error: not a valid operand
5975
6076 s_load_dwordx16 s[108:123], s[2:3], s4
61 // CHECK: error: not a valid operand
77 // GCN-ERR: error: not a valid operand
78
79 s_mov_b32 ttmp16, 0
80 // GCN-ERR: error: not a valid operand
81
82 s_mov_b32 ttmp12, 0
83 // SICIVI: error: not a valid operand
84 // GFX9: s_mov_b32 ttmp12, 0 ; encoding:
85 // GFX10: s_mov_b32 ttmp12, 0 ; encoding:
86
87 s_mov_b32 ttmp15, 0
88 // SICIVI: error: not a valid operand
89 // GFX9: s_mov_b32 ttmp15, 0 ; encoding:
90 // GFX10: s_mov_b32 ttmp15, 0 ; encoding:
91
92 s_mov_b32 flat_scratch_lo, 0
93 // SI-ERR: error: not a valid operand
94 // CIVI9: s_mov_b32 flat_scratch_lo, 0 ; encoding:
95 // GFX10-ERR: error: not a valid operand
96
97 s_mov_b32 flat_scratch_hi, 0
98 // SI-ERR: error: not a valid operand
99 // CIVI9: s_mov_b32 flat_scratch_hi, 0 ; encoding:
100 // GFX10-ERR: error: not a valid operand
101
102 s_mov_b32 tma_lo, 0
103 // SIVICI: s_mov_b32 tma_lo, 0 ; encoding:
104 // GFX9-ERR: error: not a valid operand
105 // GFX10-ERR: error: not a valid operand
106
107 s_mov_b32 tba_lo, 0
108 // SIVICI: s_mov_b32 tba_lo, 0 ; encoding:
109 // GFX9-ERR: error: not a valid operand
110 // GFX10-ERR: error: not a valid operand
44 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefix=NOSICI --check-prefix=NOSICIVI %s
55 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck --check-prefix=NOVI --check-prefix=NOSICIVI --check-prefix=NOGFX89 %s
66 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck --check-prefix=NOGFX89 %s
7
8 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding 2>&1 %s | FileCheck --check-prefix=GFX10-ERR %s
79
810 s_mov_b32 s1, s2
911 // SICI: s_mov_b32 s1, s2 ; encoding: [0x02,0x03,0x81,0xbe]
237239 s_cbranch_join s4
238240 // SICI: s_cbranch_join s4 ; encoding: [0x04,0x32,0x80,0xbe]
239241 // GFX89: s_cbranch_join s4 ; encoding: [0x04,0x2e,0x80,0xbe]
242 // GFX10-ERR: error: instruction not supported on this GPU
240243
241244 s_cbranch_join 1
242245 // NOSICI: error: invalid operand for instruction
99 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck --check-prefix=NOSICIVI --check-prefix=NOVI --check-prefix=NOGFX89 %s
1010 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck --check-prefix=NOGFX89 %s
1111
12 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding 2>&1 %s | FileCheck --check-prefix=GFX10-ERR %s
13
1214 s_add_u32 s1, s2, s3
1315 // GCN: s_add_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x80]
1416
176178 s_cbranch_g_fork s[4:5], s[6:7]
177179 // SICI: s_cbranch_g_fork s[4:5], s[6:7] ; encoding: [0x04,0x06,0x80,0x95]
178180 // GFX89: s_cbranch_g_fork s[4:5], s[6:7] ; encoding: [0x04,0x06,0x80,0x94]
181 // GFX10-ERR: error: instruction not supported on this GPU
179182
180183 s_cbranch_g_fork 1, s[6:7]
181184 // SICI: s_cbranch_g_fork 1, s[6:7] ; encoding: [0x81,0x06,0x80,0x95]
182185 // GFX89: s_cbranch_g_fork 1, s[6:7] ; encoding: [0x81,0x06,0x80,0x94]
186 // GFX10-ERR: error: instruction not supported on this GPU
183187
184188 s_cbranch_g_fork s[6:7], 2
185189 // SICI: s_cbranch_g_fork s[6:7], 2 ; encoding: [0x06,0x82,0x80,0x95]
186190 // GFX89: s_cbranch_g_fork s[6:7], 2 ; encoding: [0x06,0x82,0x80,0x94]
191 // GFX10-ERR: error: instruction not supported on this GPU
187192
188193 s_absdiff_i32 s2, s4, s6
189194 // SICI: s_absdiff_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x96]
0 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SICI %s
11 // RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
22 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICI %s
3 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX10-ERR %s
34
45 //===----------------------------------------------------------------------===//
56 // SOPC Instructions
6162
6263 s_setvskip s3, s5
6364 // GCN: s_setvskip s3, s5 ; encoding: [0x03,0x05,0x10,0xbf]
65 // GFX10-ERR: error: instruction not supported on this GPU
6466
6567 s_cmp_eq_u64 s[0:1], s[2:3]
6668 // VI: s_cmp_eq_u64 s[0:1], s[2:3] ; encoding: [0x00,0x02,0x12,0xbf]
0 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN %s
11 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI-ERR %s
22 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI-ERR %s
3 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GFX9-ERR %s
34 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX9 %s
5 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX10 %s
46
57 s_setreg_b32 0x1f803, s2
68 // GCN: error: invalid immediate: only 16-bit values are legal
2628 s_getreg_b32 s2, hwreg(3,32,32)
2729 // GCN: error: invalid bit offset: only 5-bit values are legal
2830
31 s_cbranch_i_fork s[2:3], 0x6
32 // GFX10: error: instruction not supported on this GPU
33
2934 s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES)
3035 // SI-ERR: error: invalid symbolic name of hardware register
3136 // VI-ERR: error: invalid symbolic name of hardware register
32 // GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]
37 // GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]
38 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9]
39
40 s_getreg_b32 s2, hwreg(HW_REG_TBA_LO)
41 // SI-ERR: error: invalid symbolic name of hardware register
42 // VI-ERR: error: invalid symbolic name of hardware register
43 // GFX9-ERR: error: invalid symbolic name of hardware register
44 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]
45
46 s_getreg_b32 s2, hwreg(HW_REG_TBA_HI)
47 // SI-ERR: error: invalid symbolic name of hardware register
48 // VI-ERR: error: invalid symbolic name of hardware register
49 // GFX9-ERR: error: invalid symbolic name of hardware register
50 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
51
52 s_getreg_b32 s2, hwreg(HW_REG_TMA_LO)
53 // SI-ERR: error: invalid symbolic name of hardware register
54 // VI-ERR: error: invalid symbolic name of hardware register
55 // GFX9-ERR: error: invalid symbolic name of hardware register
56 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
57
58 s_getreg_b32 s2, hwreg(HW_REG_TMA_HI)
59 // SI-ERR: error: invalid symbolic name of hardware register
60 // VI-ERR: error: invalid symbolic name of hardware register
61 // GFX9-ERR: error: invalid symbolic name of hardware register
62 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
63
64 s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO)
65 // SI-ERR: error: invalid symbolic name of hardware register
66 // VI-ERR: error: invalid symbolic name of hardware register
67 // GFX9-ERR: error: invalid symbolic name of hardware register
68 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9]
69
70 s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI)
71 // SI-ERR: error: invalid symbolic name of hardware register
72 // VI-ERR: error: invalid symbolic name of hardware register
73 // GFX9-ERR: error: invalid symbolic name of hardware register
74 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) ; encoding: [0x15,0xf8,0x02,0xb9]
75
76 s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK)
77 // SI-ERR: error: invalid symbolic name of hardware register
78 // VI-ERR: error: invalid symbolic name of hardware register
79 // GFX9-ERR: error: invalid symbolic name of hardware register
80 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK) ; encoding: [0x16,0xf8,0x02,0xb9]
81
82 s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER)
83 // SI-ERR: error: invalid symbolic name of hardware register
84 // VI-ERR: error: invalid symbolic name of hardware register
85 // GFX9-ERR: error: invalid symbolic name of hardware register
86 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER) ; encoding: [0x19,0xf8,0x02,0xb9]
3387
3488 s_cmpk_le_u32 s2, -1
3589 // GCN: error: invalid operand for instruction
11 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
22 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=VI %s
33 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=GFX9 %s
4 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=GFX10 %s
45
56 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s
67 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICIVI -check-prefix=NOSI %s
116117
117118 // HW_REG_SH_MEM_BASES valid starting from GFX9
118119 s_getreg_b32 s2, hwreg(15)
119 // SICI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x02,0xb9]
120 // VI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x82,0xb8]
121 // GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]
120 // SICI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x02,0xb9]
121 // VI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x82,0xb8]
122 // GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]
123 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9]
124
125 // GFX10+ registers
126 s_getreg_b32 s2, hwreg(16)
127 // SICI: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x02,0xb9]
128 // VI9: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x82,0xb8]
129 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]
130
131 s_getreg_b32 s2, hwreg(17)
132 // SICI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x02,0xb9]
133 // VI9: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8]
134 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
135
136 s_getreg_b32 s2, hwreg(18)
137 // SICI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x02,0xb9]
138 // VI9: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8]
139 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
140
141 s_getreg_b32 s2, hwreg(19)
142 // SICI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x02,0xb9]
143 // VI9: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8]
144 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
145
146 s_getreg_b32 s2, hwreg(20)
147 // SICI: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x02,0xb9]
148 // VI9: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x82,0xb8]
149 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9]
150
151 s_getreg_b32 s2, hwreg(21)
152 // SICI: s_getreg_b32 s2, hwreg(21) ; encoding: [0x15,0xf8,0x02,0xb9]
153 // VI9: s_getreg_b32 s2, hwreg(21) ; encoding: [0x15,0xf8,0x82,0xb8]
154 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) ; encoding: [0x15,0xf8,0x02,0xb9]
155
156 s_getreg_b32 s2, hwreg(22)
157 // SICI: s_getreg_b32 s2, hwreg(22) ; encoding: [0x16,0xf8,0x02,0xb9]
158 // VI9: s_getreg_b32 s2, hwreg(22) ; encoding: [0x16,0xf8,0x82,0xb8]
159 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK) ; encoding: [0x16,0xf8,0x02,0xb9]
160
161 s_getreg_b32 s2, hwreg(23)
162 // SICI: s_getreg_b32 s2, hwreg(23) ; encoding: [0x17,0xf8,0x02,0xb9]
163 // VI9: s_getreg_b32 s2, hwreg(23) ; encoding: [0x17,0xf8,0x82,0xb8]
164 // GFX10: s_getreg_b32 s2, hwreg(23) ; encoding: [0x17,0xf8,0x02,0xb9]
165
166 s_getreg_b32 s2, hwreg(24)
167 // SICI: s_getreg_b32 s2, hwreg(24) ; encoding: [0x18,0xf8,0x02,0xb9]
168 // VI9: s_getreg_b32 s2, hwreg(24) ; encoding: [0x18,0xf8,0x82,0xb8]
169 // GFX10: s_getreg_b32 s2, hwreg(24) ; encoding: [0x18,0xf8,0x02,0xb9]
170
171 s_getreg_b32 s2, hwreg(25)
172 // SICI: s_getreg_b32 s2, hwreg(25) ; encoding: [0x19,0xf8,0x02,0xb9]
173 // VI9: s_getreg_b32 s2, hwreg(25) ; encoding: [0x19,0xf8,0x82,0xb8]
174 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER) ; encoding: [0x19,0xf8,0x02,0xb9]
122175
123176 // raw number mapped to known HW register
124177 s_setreg_b32 0x6, s2
152205
153206 // HW_REG_SH_MEM_BASES valid starting from GFX9
154207 s_setreg_b32 hwreg(15), s2
155 // SICI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x82,0xb9]
156 // VI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x02,0xb9]
157 // GFX9: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x02,0xb9]
208 // SICI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x82,0xb9]
209 // VI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x02,0xb9]
210 // GFX9: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x02,0xb9]
211 // GFX10: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x82,0xb9]
212
213 // GFX10+ registers
214 s_setreg_b32 hwreg(16), s2
215 // SICI: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x82,0xb9]
216 // VI9: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x02,0xb9]
217 // GFX10: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x82,0xb9]
218
219 s_setreg_b32 hwreg(17), s2
220 // SICI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x82,0xb9]
221 // VI9: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
222 // GFX10: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x82,0xb9]
223
224 s_setreg_b32 hwreg(18), s2
225 // SICI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x82,0xb9]
226 // VI9: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
227 // GFX10: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x82,0xb9]
228
229 s_setreg_b32 hwreg(19), s2
230 // SICI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x82,0xb9]
231 // VI9: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
232 // GFX10: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x82,0xb9]
233
234 s_setreg_b32 hwreg(20), s2
235 // SICI: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x82,0xb9]
236 // VI9: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x02,0xb9]
237 // GFX10: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; encoding: [0x14,0xf8,0x82,0xb9]
238
239 s_setreg_b32 hwreg(21), s2
240 // SICI: s_setreg_b32 hwreg(21), s2 ; encoding: [0x15,0xf8,0x82,0xb9]
241 // VI9: s_setreg_b32 hwreg(21), s2 ; encoding: [0x15,0xf8,0x02,0xb9]
242 // GFX10: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s2 ; encoding: [0x15,0xf8,0x82,0xb9]
243
244 s_setreg_b32 hwreg(22), s2
245 // SICI: s_setreg_b32 hwreg(22), s2 ; encoding: [0x16,0xf8,0x82,0xb9]
246 // VI9: s_setreg_b32 hwreg(22), s2 ; encoding: [0x16,0xf8,0x02,0xb9]
247 // GFX10: s_setreg_b32 hwreg(HW_REG_XNACK_MASK), s2 ; encoding: [0x16,0xf8,0x82,0xb9]
248
249 s_setreg_b32 hwreg(23), s2
250 // SICI: s_setreg_b32 hwreg(23), s2 ; encoding: [0x17,0xf8,0x82,0xb9]
251 // VI9: s_setreg_b32 hwreg(23), s2 ; encoding: [0x17,0xf8,0x02,0xb9]
252 // GFX10: s_setreg_b32 hwreg(23), s2 ; encoding: [0x17,0xf8,0x82,0xb9]
253
254 s_setreg_b32 hwreg(24), s2
255 // SICI: s_setreg_b32 hwreg(24), s2 ; encoding: [0x18,0xf8,0x82,0xb9]
256 // VI9: s_setreg_b32 hwreg(24), s2 ; encoding: [0x18,0xf8,0x02,0xb9]
257 // GFX10: s_setreg_b32 hwreg(24), s2 ; encoding: [0x18,0xf8,0x82,0xb9]
258
259 s_setreg_b32 hwreg(25), s2
260 // SICI: s_setreg_b32 hwreg(25), s2 ; encoding: [0x19,0xf8,0x82,0xb9]
261 // VI9: s_setreg_b32 hwreg(25), s2 ; encoding: [0x19,0xf8,0x02,0xb9]
262 // GFX10: s_setreg_b32 hwreg(HW_REG_POPS_PACKER), s2 ; encoding: [0x19,0xf8,0x82,0xb9]
158263
159264 // HW register code, non-default offset/width
160265 s_setreg_b32 hwreg(5, 1, 31), s2
193193 s_sendmsg 0x4
194194 // GCN: s_sendmsg 4 ; encoding: [0x04,0x00,0x90,0xbf]
195195
196 s_sendmsg 9
197 // GCN: s_sendmsg 9 ; encoding: [0x09,0x00,0x90,0xbf]
198
196199 s_sendmsg 11
197200 // GCN: s_sendmsg 11 ; encoding: [0x0b,0x00,0x90,0xbf]
198201