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[CostModel] Add SK_ExtractSubvector handling to getInstructionThroughput (PR39368) Add ShuffleVectorInst::isExtractSubvectorMask helper to match shuffle masks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346510 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 11 months ago
4 changed file(s) with 92 addition(s) and 38 deletion(s). Raw diff Collapse all Expand all
26472647 return !changesLength() && isTransposeMask(getMask());
26482648 }
26492649
2650 /// Return true if this shuffle mask is an extract subvector mask.
2651 /// A valid extract subvector mask returns a smaller vector from a single
2652 /// source operand. The base extraction index is returned as well.
2653 static bool isExtractSubvectorMask(ArrayRef Mask, int NumSrcElts,
2654 int &Index);
2655 static bool isExtractSubvectorMask(const Constant *Mask, int NumSrcElts,
2656 int &Index) {
2657 assert(Mask->getType()->isVectorTy() && "Shuffle needs vector constant.");
2658 SmallVector MaskAsInts;
2659 getShuffleMask(Mask, MaskAsInts);
2660 return isExtractSubvectorMask(MaskAsInts, NumSrcElts, Index);
2661 }
2662
2663 /// Return true if this shuffle mask is an extract subvector mask.
2664 bool isExtractSubvectorMask(int &Index) const {
2665 int NumSrcElts = Op<0>()->getType()->getVectorNumElements();
2666 return isExtractSubvectorMask(getMask(), NumSrcElts, Index);
2667 }
2668
26502669 /// Change values in a shuffle permute mask assuming the two vector operands
26512670 /// of length InVecNumElts have swapped position.
26522671 static void commuteShuffleMask(MutableArrayRef Mask,
11071107 }
11081108 case Instruction::ShuffleVector: {
11091109 const ShuffleVectorInst *Shuffle = cast(I);
1110 // TODO: Identify and add costs for insert/extract subvector, etc.
1110 Type *Ty = Shuffle->getType();
1111 Type *SrcTy = Shuffle->getOperand(0)->getType();
1112
1113 // TODO: Identify and add costs for insert subvector, etc.
1114 int SubIndex;
1115 if (Shuffle->isExtractSubvectorMask(SubIndex))
1116 return TTIImpl->getShuffleCost(SK_ExtractSubvector, Ty, SubIndex, SrcTy);
1117
11111118 if (Shuffle->changesLength())
11121119 return -1;
11131120
11141121 if (Shuffle->isIdentity())
11151122 return 0;
11161123
1117 Type *Ty = Shuffle->getType();
11181124 if (Shuffle->isReverse())
11191125 return TTIImpl->getShuffleCost(SK_Reverse, Ty, 0, nullptr);
11201126
17951795 return false;
17961796 }
17971797 return true;
1798 }
1799
1800 bool ShuffleVectorInst::isExtractSubvectorMask(ArrayRef Mask,
1801 int NumSrcElts, int &Index) {
1802 // Must extract from a single source.
1803 if (!isSingleSourceMaskImpl(Mask, NumSrcElts))
1804 return false;
1805
1806 // Must be smaller (else this is an Identity shuffle).
1807 if (NumSrcElts <= Mask.size())
1808 return false;
1809
1810 // Find start of extraction, accounting that we may start with an UNDEF.
1811 int SubIndex = -1;
1812 for (int i = 0, e = Mask.size(); i != e; ++i) {
1813 int M = Mask[i];
1814 if (M < 0)
1815 continue;
1816 int Offset = (M % NumSrcElts) - i;
1817 if (0 <= SubIndex && SubIndex != Offset)
1818 return false;
1819 SubIndex = Offset;
1820 }
1821
1822 if (0 <= SubIndex) {
1823 Index = SubIndex;
1824 return true;
1825 }
1826 return false;
17981827 }
17991828
18001829 bool ShuffleVectorInst::isIdentityWithPadding() const {
1717
1818 define void @test_vXf64(<4 x double> %src256, <8 x double> %src512) {
1919 ; CHECK-LABEL: 'test_vXf64'
20 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V256_01 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32>
21 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V256_23 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32>
22 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_01 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
23 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_23 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
24 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_45 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
25 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_67 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
26 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_0123 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32>
27 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_2345 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32>
28 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_4567 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32> >
20 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256_01 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32> >
21 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256_23 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32>
22 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_01 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
23 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_23 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
24 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_45 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
25 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_67 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
26 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_0123 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32>
27 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_2345 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32>
28 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_4567 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32>
2929 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
3030 ;
3131 ; BTVER2-LABEL: 'test_vXf64'
32 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V256_01 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32>
33 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V256_23 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32>
34 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_01 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
35 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_23 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
36 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_45 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
37 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_67 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
38 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_0123 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32>
39 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_2345 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32>
40 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_4567 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32> >
32 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256_01 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32> >
33 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256_23 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32>
34 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_01 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
35 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_23 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
36 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_45 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
37 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_67 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32>
38 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_0123 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32>
39 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_2345 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32>
40 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_4567 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32>
4141 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
4242 ;
4343 %V256_01 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32>
5454
5555 define void @test_vXfi64(<4 x i64> %src256, <8 x i64> %src512) {
5656 ; CHECK-LABEL: 'test_vXfi64'
57 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V256_01 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32>
58 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V256_23 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32>
59 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_01 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
60 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_23 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
61 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_45 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
62 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_67 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
63 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_0123 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32>
64 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_2345 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32>
65 ; CHECK-NEXT: Cost Model: Unknown cost for instruction: %V512_4567 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32> >
57 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256_01 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32> >
58 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256_23 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32>
59 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_01 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
60 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_23 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
61 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_45 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
62 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_67 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
63 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_0123 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32>
64 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_2345 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32>
65 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_4567 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32>
6666 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
6767 ;
6868 ; BTVER2-LABEL: 'test_vXfi64'
69 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V256_01 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32>
70 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V256_23 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32>
71 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_01 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
72 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_23 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
73 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_45 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
74 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_67 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
75 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_0123 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32>
76 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_2345 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32>
77 ; BTVER2-NEXT: Cost Model: Unknown cost for instruction: %V512_4567 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32> >
69 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256_01 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32> >
70 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256_23 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32>
71 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_01 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
72 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_23 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
73 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_45 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
74 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_67 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32>
75 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_0123 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32>
76 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_2345 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32>
77 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512_4567 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32>
7878 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
7979 ;
8080 %V256_01 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32>