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[X86] Add BMI2 scheduling tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308136 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 3 years ago
1 changed file(s) with 180 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mattr=+bmi2 | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=knl | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=CHECK --check-prefix=ZNVER1
6
7 define i32 @test_bzhi_i32(i32 %a0, i32 %a1, i32 *%a2) {
8 ; GENERIC-LABEL: test_bzhi_i32:
9 ; GENERIC: # BB#0:
10 ; GENERIC-NEXT: bzhil %edi, (%rdx), %ecx
11 ; GENERIC-NEXT: bzhil %edi, %esi, %eax
12 ; GENERIC-NEXT: addl %ecx, %eax
13 ; GENERIC-NEXT: retq
14 ;
15 ; HASWELL-LABEL: test_bzhi_i32:
16 ; HASWELL: # BB#0:
17 ; HASWELL-NEXT: bzhil %edi, (%rdx), %ecx # sched: [4:0.50]
18 ; HASWELL-NEXT: bzhil %edi, %esi, %eax # sched: [1:0.50]
19 ; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
20 ; HASWELL-NEXT: retq # sched: [1:1.00]
21 ;
22 ; ZNVER1-LABEL: test_bzhi_i32:
23 ; ZNVER1: # BB#0:
24 ; ZNVER1-NEXT: bzhil %edi, (%rdx), %ecx # sched: [?:0.000000e+00]
25 ; ZNVER1-NEXT: bzhil %edi, %esi, %eax # sched: [?:0.000000e+00]
26 ; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.50]
27 ; ZNVER1-NEXT: retq # sched: [4:1.00]
28 %1 = load i32, i32 *%a2
29 %2 = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %1, i32 %a0)
30 %3 = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %a1, i32 %a0)
31 %4 = add i32 %2, %3
32 ret i32 %4
33 }
34 declare i32 @llvm.x86.bmi.bzhi.32(i32, i32)
35
36 define i64 @test_bzhi_i64(i64 %a0, i64 %a1, i64 *%a2) {
37 ; GENERIC-LABEL: test_bzhi_i64:
38 ; GENERIC: # BB#0:
39 ; GENERIC-NEXT: bzhiq %rdi, (%rdx), %rcx
40 ; GENERIC-NEXT: bzhiq %rdi, %rsi, %rax
41 ; GENERIC-NEXT: addq %rcx, %rax
42 ; GENERIC-NEXT: retq
43 ;
44 ; HASWELL-LABEL: test_bzhi_i64:
45 ; HASWELL: # BB#0:
46 ; HASWELL-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [4:0.50]
47 ; HASWELL-NEXT: bzhiq %rdi, %rsi, %rax # sched: [1:0.50]
48 ; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
49 ; HASWELL-NEXT: retq # sched: [1:1.00]
50 ;
51 ; ZNVER1-LABEL: test_bzhi_i64:
52 ; ZNVER1: # BB#0:
53 ; ZNVER1-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [?:0.000000e+00]
54 ; ZNVER1-NEXT: bzhiq %rdi, %rsi, %rax # sched: [?:0.000000e+00]
55 ; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.50]
56 ; ZNVER1-NEXT: retq # sched: [4:1.00]
57 %1 = load i64, i64 *%a2
58 %2 = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %1, i64 %a0)
59 %3 = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %a1, i64 %a0)
60 %4 = add i64 %2, %3
61 ret i64 %4
62 }
63 declare i64 @llvm.x86.bmi.bzhi.64(i64, i64)
64
65 define i32 @test_pdep_i32(i32 %a0, i32 %a1, i32 *%a2) {
66 ; GENERIC-LABEL: test_pdep_i32:
67 ; GENERIC: # BB#0:
68 ; GENERIC-NEXT: pdepl (%rdx), %edi, %ecx
69 ; GENERIC-NEXT: pdepl %esi, %edi, %eax
70 ; GENERIC-NEXT: addl %ecx, %eax
71 ; GENERIC-NEXT: retq
72 ;
73 ; HASWELL-LABEL: test_pdep_i32:
74 ; HASWELL: # BB#0:
75 ; HASWELL-NEXT: pdepl (%rdx), %edi, %ecx # sched: [7:1.00]
76 ; HASWELL-NEXT: pdepl %esi, %edi, %eax # sched: [3:1.00]
77 ; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
78 ; HASWELL-NEXT: retq # sched: [1:1.00]
79 ;
80 ; ZNVER1-LABEL: test_pdep_i32:
81 ; ZNVER1: # BB#0:
82 ; ZNVER1-NEXT: pdepl (%rdx), %edi, %ecx # sched: [?:0.000000e+00]
83 ; ZNVER1-NEXT: pdepl %esi, %edi, %eax # sched: [?:0.000000e+00]
84 ; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.50]
85 ; ZNVER1-NEXT: retq # sched: [4:1.00]
86 %1 = load i32, i32 *%a2
87 %2 = tail call i32 @llvm.x86.bmi.pdep.32(i32 %a0, i32 %1)
88 %3 = tail call i32 @llvm.x86.bmi.pdep.32(i32 %a0, i32 %a1)
89 %4 = add i32 %2, %3
90 ret i32 %4
91 }
92 declare i32 @llvm.x86.bmi.pdep.32(i32, i32)
93
94 define i64 @test_pdep_i64(i64 %a0, i64 %a1, i64 *%a2) {
95 ; GENERIC-LABEL: test_pdep_i64:
96 ; GENERIC: # BB#0:
97 ; GENERIC-NEXT: pdepq (%rdx), %rdi, %rcx
98 ; GENERIC-NEXT: pdepq %rsi, %rdi, %rax
99 ; GENERIC-NEXT: addq %rcx, %rax
100 ; GENERIC-NEXT: retq
101 ;
102 ; HASWELL-LABEL: test_pdep_i64:
103 ; HASWELL: # BB#0:
104 ; HASWELL-NEXT: pdepq (%rdx), %rdi, %rcx # sched: [7:1.00]
105 ; HASWELL-NEXT: pdepq %rsi, %rdi, %rax # sched: [3:1.00]
106 ; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
107 ; HASWELL-NEXT: retq # sched: [1:1.00]
108 ;
109 ; ZNVER1-LABEL: test_pdep_i64:
110 ; ZNVER1: # BB#0:
111 ; ZNVER1-NEXT: pdepq (%rdx), %rdi, %rcx # sched: [?:0.000000e+00]
112 ; ZNVER1-NEXT: pdepq %rsi, %rdi, %rax # sched: [?:0.000000e+00]
113 ; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.50]
114 ; ZNVER1-NEXT: retq # sched: [4:1.00]
115 %1 = load i64, i64 *%a2
116 %2 = tail call i64 @llvm.x86.bmi.pdep.64(i64 %a0, i64 %1)
117 %3 = tail call i64 @llvm.x86.bmi.pdep.64(i64 %a0, i64 %a1)
118 %4 = add i64 %2, %3
119 ret i64 %4
120 }
121 declare i64 @llvm.x86.bmi.pdep.64(i64, i64)
122
123 define i32 @test_pext_i32(i32 %a0, i32 %a1, i32 *%a2) {
124 ; GENERIC-LABEL: test_pext_i32:
125 ; GENERIC: # BB#0:
126 ; GENERIC-NEXT: pextl (%rdx), %edi, %ecx
127 ; GENERIC-NEXT: pextl %esi, %edi, %eax
128 ; GENERIC-NEXT: addl %ecx, %eax
129 ; GENERIC-NEXT: retq
130 ;
131 ; HASWELL-LABEL: test_pext_i32:
132 ; HASWELL: # BB#0:
133 ; HASWELL-NEXT: pextl (%rdx), %edi, %ecx # sched: [7:1.00]
134 ; HASWELL-NEXT: pextl %esi, %edi, %eax # sched: [3:1.00]
135 ; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
136 ; HASWELL-NEXT: retq # sched: [1:1.00]
137 ;
138 ; ZNVER1-LABEL: test_pext_i32:
139 ; ZNVER1: # BB#0:
140 ; ZNVER1-NEXT: pextl (%rdx), %edi, %ecx # sched: [?:0.000000e+00]
141 ; ZNVER1-NEXT: pextl %esi, %edi, %eax # sched: [?:0.000000e+00]
142 ; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.50]
143 ; ZNVER1-NEXT: retq # sched: [4:1.00]
144 %1 = load i32, i32 *%a2
145 %2 = tail call i32 @llvm.x86.bmi.pext.32(i32 %a0, i32 %1)
146 %3 = tail call i32 @llvm.x86.bmi.pext.32(i32 %a0, i32 %a1)
147 %4 = add i32 %2, %3
148 ret i32 %4
149 }
150 declare i32 @llvm.x86.bmi.pext.32(i32, i32)
151
152 define i64 @test_pext_i64(i64 %a0, i64 %a1, i64 *%a2) {
153 ; GENERIC-LABEL: test_pext_i64:
154 ; GENERIC: # BB#0:
155 ; GENERIC-NEXT: pextq (%rdx), %rdi, %rcx
156 ; GENERIC-NEXT: pextq %rsi, %rdi, %rax
157 ; GENERIC-NEXT: addq %rcx, %rax
158 ; GENERIC-NEXT: retq
159 ;
160 ; HASWELL-LABEL: test_pext_i64:
161 ; HASWELL: # BB#0:
162 ; HASWELL-NEXT: pextq (%rdx), %rdi, %rcx # sched: [7:1.00]
163 ; HASWELL-NEXT: pextq %rsi, %rdi, %rax # sched: [3:1.00]
164 ; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
165 ; HASWELL-NEXT: retq # sched: [1:1.00]
166 ;
167 ; ZNVER1-LABEL: test_pext_i64:
168 ; ZNVER1: # BB#0:
169 ; ZNVER1-NEXT: pextq (%rdx), %rdi, %rcx # sched: [?:0.000000e+00]
170 ; ZNVER1-NEXT: pextq %rsi, %rdi, %rax # sched: [?:0.000000e+00]
171 ; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.50]
172 ; ZNVER1-NEXT: retq # sched: [4:1.00]
173 %1 = load i64, i64 *%a2
174 %2 = tail call i64 @llvm.x86.bmi.pext.64(i64 %a0, i64 %1)
175 %3 = tail call i64 @llvm.x86.bmi.pext.64(i64 %a0, i64 %a1)
176 %4 = add i64 %2, %3
177 ret i64 %4
178 }
179 declare i64 @llvm.x86.bmi.pext.64(i64, i64)