llvm.org GIT mirror llvm / 3cafbf7
Add sub-registers sets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36278 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
2 changed file(s) with 79 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
4040 // Aliases - A list of registers that this register overlaps with. A read or
4141 // modification of this register can potentially read or modify the aliased
4242 // registers.
43 //
4443 list Aliases = [];
4544
45 // SubRegs - A list of registers that are parts of this register. Note these
46 // are "immediate" sub-registers and the registers within the list do not
47 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
48 // not [AX, AH, AL].
49 list SubRegs = [];
50
4651 // DwarfNumber - Number used internally by gcc/gdb to identify the register.
4752 // These values can be determined by locating the .h file in the
4853 // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The
4954 // order of these names correspond to the enumeration used by gcc. A value of
5055 // -1 indicates that the gcc number is undefined.
5156 int DwarfNumber = -1;
57 }
58
59 // RegisterWithSubRegs - This can be used to define instances of Register which
60 // need to specify sub-registers.
61 // List "subregs" specifies which registers are sub-registers to this one. This
62 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
63 // This allows the code generator to be careful not to put two values with
64 // overlapping live ranges into registers which alias.
65 class RegisterWithSubRegs subregs> : Register {
66 let SubRegs = subregs;
5267 }
5368
5469 // RegisterGroup - This can be used to define instances of Register which
104104 return false;
105105 }
106106 return true;
107 }
108
109 static void addSubReg(Record *R, Record *S,
110 std::map > &SubRegs,
111 std::map > &Aliases,
112 RegisterInfoEmitter &RIE) {
113 if (R == S) {
114 cerr << "Error: recursive sub-register relationship between"
115 << " register " << RIE.getQualifiedName(R)
116 << " and its sub-registers?\n";
117 abort();
118 }
119
120 if (!SubRegs[R].insert(S).second)
121 return;
122 Aliases[R].insert(S);
123 Aliases[S].insert(R);
124 if (SubRegs.count(S))
125 for (std::set::iterator I = SubRegs[S].begin(),
126 E = SubRegs[S].end(); I != E; ++I)
127 addSubReg(R, *I, SubRegs, Aliases, RIE);
107128 }
108129
109130 // RegisterInfoEmitter::run - Main register file description emitter.
272293 << "RegClass,\n";
273294 OS << " };\n";
274295
275 // Emit register class aliases...
296 // Emit register sub-registers / aliases...
297 std::map > RegisterSubRegs;
276298 std::map > RegisterAliases;
277299 const std::vector &Regs = Target.getRegisters();
278300
297319 }
298320 }
299321
322 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
323 Record *R = Regs[i].TheDef;
324 std::vector LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
325 // Process sub-register set and add aliases information.
326 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
327 Record *SubReg = LI[j];
328 if (RegisterSubRegs[R].count(SubReg))
329 cerr << "Warning: register " << getQualifiedName(SubReg)
330 << " specified as a sub-register of " << getQualifiedName(R)
331 << " multiple times!\n";
332 addSubReg(R, SubReg, RegisterSubRegs, RegisterAliases, *this);
333 }
334 }
335
300336 if (!RegisterAliases.empty())
301337 OS << "\n\n // Register Alias Sets...\n";
302338
313349 OS << "0 };\n";
314350 }
315351
352 if (!RegisterSubRegs.empty())
353 OS << "\n\n // Register Sub-registers Sets...\n";
354
355 // Emit the empty sub-registers list
356 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
357 // Loop over all of the registers which have sub-registers, emitting the
358 // sub-registers list to memory.
359 for (std::map >::iterator
360 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
361 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
362 for (std::set::iterator ASI = I->second.begin(),
363 E = I->second.end(); ASI != E; ++ASI)
364 OS << getQualifiedName(*ASI) << ", ";
365 OS << "0 };\n";
366 }
316367 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
317 OS << " { \"NOREG\",\t0 },\n";
318
319
320 // Now that register alias sets have been emitted, emit the register
321 // descriptors now.
368 OS << " { \"NOREG\",\t0,\t0 },\n";
369
370
371 // Now that register alias and sub-registers sets have been emitted, emit the
372 // register descriptors now.
322373 const std::vector &Registers = Target.getRegisters();
323374 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
324375 const CodeGenRegister &Reg = Registers[i];
329380 OS << Reg.getName();
330381 OS << "\",\t";
331382 if (RegisterAliases.count(Reg.TheDef))
332 OS << Reg.getName() << "_AliasSet },\n";
383 OS << Reg.getName() << "_AliasSet,\t";
333384 else
334 OS << "Empty_AliasSet },\n";
385 OS << "Empty_AliasSet,\t";
386 if (RegisterSubRegs.count(Reg.TheDef))
387 OS << Reg.getName() << "_SubRegsSet },\n";
388 else
389 OS << "Empty_SubRegsSet },\n";
335390 }
336391 OS << " };\n"; // End of register descriptors...
337392 OS << "}\n\n"; // End of anonymous namespace...