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[ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2 Differential Revision: http://reviews.llvm.org/D11055 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241800 91177308-0d34-0410-b5e6-96231b3b80d8 Scott Douglass 5 years ago
2 changed file(s) with 16 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
54665466 CanAcceptPredicationCode = true;
54675467 }
54685468
5469 // \brief Some Thumb1 instructions have two operand forms that are not
5469 // \brief Some Thumb instructions have two operand forms that are not
54705470 // available as three operand, convert to two operand form if possible.
54715471 //
54725472 // FIXME: We would really like to be able to tablegen'erate this.
54735473 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
54745474 bool CarrySetting,
54755475 OperandVector &Operands) {
5476 if (Operands.size() != 6 || !isThumbOne())
5476 if (Operands.size() != 6)
54775477 return;
54785478
54795479 ARMOperand &Op3 = static_cast(*Operands[3]);
54815481 if (!Op3.isReg() || !Op4.isReg())
54825482 return;
54835483
5484 // For most Thumb2 cases we just generate the 3 operand form and reduce
5485 // it in processInstruction(), but for ADD involving PC the the 3 operand
5486 // form won't accept PC so we do the transformation here.
54845487 ARMOperand &Op5 = static_cast(*Operands[5]);
5488 if (isThumbTwo()) {
5489 if (Mnemonic != "add" ||
5490 !(Op3.getReg() == ARM::PC || Op4.getReg() == ARM::PC ||
5491 (Op5.isReg() && Op5.getReg() == ARM::PC)))
5492 return;
5493 } else if (!isThumbOne())
5494 return;
54855495
54865496 if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
54875497 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
6464
6565 ADD r3, r3, r1 // T2
6666 // CHECK: add r3, r1 @ encoding: [0x0b,0x44]
67 ADD r4, r4, pc // T2
68 // CHECK: add r4, pc @ encoding: [0x7c,0x44]
69 ADD pc, pc, r2 // T2
70 // CHECK: add pc, r2 @ encoding: [0x97,0x44]
6771
6872 // ADD (SP plus immediate) A8.8.9
6973 ADD sp, sp, #20 // T2