llvm.org GIT mirror llvm / 3c55c54
- Use xor to clear integer registers (set R, 0). - Added a new format for instructions where the source register is implied and it is same as the destination register. Used for pseudo instructions that clear the destination register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25872 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 14 years ago
4 changed file(s) with 41 addition(s) and 19 deletion(s). Raw diff Collapse all Expand all
109109 "FPFormBits",
110110 "Opcode"];
111111 let TSFlagsShifts = [0,
112 5,
113112 6,
114 10,
115 12,
116 16];
113 7,
114 11,
115 13,
116 17];
117117 }
118118
119119 // The X86 target supports two different syntaxes for emitting machine code.
472472
473473 case X86II::MRMSrcReg:
474474 MCE.emitByte(BaseOpcode);
475
476475 emitRegModRMByte(MI.getOperand(1).getReg(),
477476 getX86RegNum(MI.getOperand(0).getReg()));
478477 if (MI.getNumOperands() == 3)
517516 assert(0 && "Unknown operand!");
518517 }
519518 break;
520 }
521 }
519
520 case X86II::MRMInitReg:
521 MCE.emitByte(BaseOpcode);
522 emitRegModRMByte(MI.getOperand(0).getReg(),
523 getX86RegNum(MI.getOperand(0).getReg()));
524 break;
525 }
526 }
7474 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
7575 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
7676
77 FormMask = 31,
77 // MRMInitReg - This form is used for instructions whose source and
78 // destinations are the same register.
79 MRMInitReg = 32,
80
81 FormMask = 63,
7882
7983 //===------------------------------------------------------------------===//
8084 // Actual flags...
8286 // OpSize - Set if this instruction requires an operand size prefix (0x66),
8387 // which most often indicates that the instruction operates on 16 bit data
8488 // instead of 32 bit data.
85 OpSize = 1 << 5,
89 OpSize = 1 << 6,
8690
8791 // Op0Mask - There are several prefix bytes that are used to form two byte
8892 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
8993 // used to obtain the setting of this field. If no bits in this field is
9094 // set, there is no prefix byte for obtaining a multibyte opcode.
9195 //
92 Op0Shift = 6,
96 Op0Shift = 7,
9397 Op0Mask = 0xF << Op0Shift,
9498
9599 // TB - TwoByte - Set if this instruction has a two byte opcode, which
114118 //===------------------------------------------------------------------===//
115119 // This two-bit field describes the size of an immediate operand. Zero is
116120 // unused so that we can tell if we forgot to set a value.
117 ImmShift = 10,
121 ImmShift = 11,
118122 ImmMask = 7 << ImmShift,
119123 Imm8 = 1 << ImmShift,
120124 Imm16 = 2 << ImmShift,
124128 // FP Instruction Classification... Zero is non-fp instruction.
125129
126130 // FPTypeMask - Mask for all of the FP types...
127 FPTypeShift = 12,
131 FPTypeShift = 13,
128132 FPTypeMask = 7 << FPTypeShift,
129133
130134 // NotFP - The default, set for instructions that do not use FP registers.
157161 SpecialFP = 7 << FPTypeShift,
158162
159163 // Bit 15 is unused.
160 OpcodeShift = 16,
164 OpcodeShift = 17,
161165 OpcodeMask = 0xFF << OpcodeShift,
162 // Bits 24 -> 31 are unused
166 // Bits 25 -> 31 are unused
163167 };
164168 }
165169
179179 // Format specifies the encoding used by the instruction. This is part of the
180180 // ad-hoc solution used to emit machine instruction encodings by our machine
181181 // code emitter.
182 class Format val> {
183 bits<5> Value = val;
182 class Format val> {
183 bits<6> Value = val;
184184 }
185185
186186 def Pseudo : Format<0>; def RawFrm : Format<1>;
193193 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
194194 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
195195 def MRM6m : Format<30>; def MRM7m : Format<31>;
196 def MRMInitReg : Format<32>;
196197
197198 //===----------------------------------------------------------------------===//
198199 // X86 Instruction Predicate Definitions.
237238
238239 bits<8> Opcode = opcod;
239240 Format Form = f;
240 bits<5> FormBits = Form.Value;
241 bits<6> FormBits = Form.Value;
241242 ImmType ImmT = i;
242243 bits<2> ImmTypeBits = ImmT.Value;
243244
707708 "mov{l} {$src, $dst|$dst, $src}",
708709 [(store R32:$src, addr:$dst)]>;
709710
711 // Pseudo-instructions that map movr0 to xor.
712 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
713 def MOV8r0 : I<0x30, MRMInitReg, (ops R8 :$dst),
714 "xor{b} $dst, $dst",
715 [(set R8:$dst, 0)]>;
716 def MOV16r0 : I<0x31, MRMInitReg, (ops R16:$dst),
717 "xor{w} $dst, $dst",
718 [(set R16:$dst, 0)]>, OpSize;
719 def MOV32r0 : I<0x31, MRMInitReg, (ops R32:$dst),
720 "xor{l} $dst, $dst",
721 [(set R32:$dst, 0)]>;
722
710723 //===----------------------------------------------------------------------===//
711724 // Fixed-Register Multiplication and Division Instructions...
712725 //
24772490
24782491 // Pseudo-instructions that map fld0 to xorps/xorpd for sse.
24792492 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2480 def FLD0SS : I<0x57, MRMSrcReg, (ops FR32:$dst),
2493 def FLD0SS : I<0x57, MRMInitReg, (ops FR32:$dst),
24812494 "xorps $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
24822495 Requires<[HasSSE1]>, TB;
2483 def FLD0SD : I<0x57, MRMSrcReg, (ops FR64:$dst),
2496 def FLD0SD : I<0x57, MRMInitReg, (ops FR64:$dst),
24842497 "xorpd $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
24852498 Requires<[HasSSE2]>, TB, OpSize;
24862499