llvm.org GIT mirror llvm / 3c221ac
Merge in PPC internal-as fixes: r167861, r167862, r167863, r167875, r167860, r167864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168351 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 6 years ago
6 changed file(s) with 100 addition(s) and 33 deletion(s). Raw diff Collapse all Expand all
456456 R_PPC_REL14 = 11,
457457 R_PPC_REL14_BRTAKEN = 12,
458458 R_PPC_REL14_BRNTAKEN = 13,
459 R_PPC_REL32 = 26
459 R_PPC_REL32 = 26,
460 R_PPC_TPREL16_LO = 70,
461 R_PPC_TPREL16_HA = 72
460462 };
461463
462464 // ELF Relocation types for PPC64
7373 Type = ELF::R_PPC_ADDR14; // XXX: or BRNTAKEN?_
7474 break;
7575 case PPC::fixup_ppc_ha16:
76 Type = ELF::R_PPC_ADDR16_HA;
76 switch (Modifier) {
77 default: llvm_unreachable("Unsupported Modifier");
78 case MCSymbolRefExpr::VK_PPC_TPREL16_HA:
79 Type = ELF::R_PPC_TPREL16_HA;
80 break;
81 case MCSymbolRefExpr::VK_None:
82 Type = ELF::R_PPC_ADDR16_HA;
83 break;
84 }
7785 break;
7886 case PPC::fixup_ppc_lo16:
79 Type = ELF::R_PPC_ADDR16_LO;
87 switch (Modifier) {
88 default: llvm_unreachable("Unsupported Modifier");
89 case MCSymbolRefExpr::VK_PPC_TPREL16_LO:
90 Type = ELF::R_PPC_TPREL16_LO;
91 break;
92 case MCSymbolRefExpr::VK_None:
93 Type = ELF::R_PPC_ADDR16_LO;
94 break;
95 }
8096 break;
8197 case PPC::fixup_ppc_lo14:
8298 Type = ELF::R_PPC_ADDR14;
233233
234234 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
235235 let Defs = [CTR8], Uses = [CTR8] in {
236 def BDZ8 : IForm_ext<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
237 "bdz $dst", BrB, []>;
238 def BDNZ8 : IForm_ext<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
239 "bdnz $dst", BrB, []>;
236 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
237 "bdz $dst">;
238 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
239 "bdnz $dst">;
240240 }
241241 }
242242
510510 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
511511 []>;
512512
513 def ISEL8 : AForm_1<31, 15,
513 def ISEL8 : AForm_4<31, 15,
514514 (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB, pred:$cond),
515515 "isel $rT, $rA, $rB, $cond", IntGeneral,
516516 []>;
555555 "lhaux $rD, $addr", LdStLHAU,
556556 []>, RegConstraint<"$addr.offreg = $ea_result">,
557557 NoEncode<"$ea_result">;
558 def LWAUX : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc:$ea_result),
558 def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc:$ea_result),
559559 (ins memrr:$addr),
560560 "lwaux $rD, $addr", LdStLHAU,
561561 []>, RegConstraint<"$addr.offreg = $ea_result">,
605605 "lbzux $rD, $addr", LdStLoadUpd,
606606 []>, RegConstraint<"$addr.offreg = $ea_result">,
607607 NoEncode<"$ea_result">;
608 def LHZUX8 : XForm_1<31, 331, (outs G8RC:$rD, ptr_rc:$ea_result),
608 def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc:$ea_result),
609609 (ins memrr:$addr),
610610 "lhzux $rD, $addr", LdStLoadUpd,
611611 []>, RegConstraint<"$addr.offreg = $ea_result">,
705705
706706 let PPC970_Unit = 2 in {
707707
708 def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
708 def STBU8 : DForm_1a<39, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
709709 symbolLo:$ptroff, ptr_rc:$ptrreg),
710710 "stbu $rS, $ptroff($ptrreg)", LdStStoreUpd,
711711 [(set ptr_rc:$ea_res,
9393 let Inst{31} = lk;
9494 }
9595
96 class IForm_ext opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
97 string asmstr, InstrItinClass itin, list pattern>
98 : IForm {
99 let LI{0-4} = bo;
100 }
101
10296 // 1.7.2 B-Form
10397 class BForm opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
10498 : I {
117111 let Inst{31} = lk;
118112 }
119113
114 class BForm_1 opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
115 string asmstr>
116 : BForm {
117 let BIBO{4-0} = bo;
118 let BIBO{6-5} = 0;
119 let CR = 0;
120 }
120121
121122 // 1.7.4 D-Form
122123 class DForm_base opcode, dag OOL, dag IOL, string asmstr,
624625 InstrItinClass itin>
625626 : I {
626627 bits<8> FXM;
627 bits<5> ST;
628 bits<5> rS;
628629
629 let Inst{6-10} = ST;
630 let Inst{6-10} = rS;
630631 let Inst{11} = 0;
631632 let Inst{12-19} = FXM;
632633 let Inst{20} = 0;
665666 string cstr, InstrItinClass itin, listpattern>
666667 : I {
667668 bits<8> FM;
668 bits<5> RT;
669 bits<5> rT;
669670
670671 bit RC = 0; // set by isDOT
671672 let Pattern = pattern;
674675 let Inst{6} = 0;
675676 let Inst{7-14} = FM;
676677 let Inst{15} = 0;
677 let Inst{16-20} = RT;
678 let Inst{16-20} = rT;
678679 let Inst{21-30} = xo;
679680 let Inst{31} = RC;
680681 }
755756 InstrItinClass itin, list pattern>
756757 : AForm_1 {
757758 let FRB = 0;
759 }
760
761 class AForm_4 opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
762 InstrItinClass itin, list pattern>
763 : I {
764 bits<5> RT;
765 bits<5> RA;
766 bits<5> RB;
767 bits<7> BIBO; // 2 bits of BI and 5 bits of BO (must be 12).
768 bits<3> CR;
769
770 let Pattern = pattern;
771
772 let Inst{6-10} = RT;
773 let Inst{11-15} = RA;
774 let Inst{16-20} = RB;
775 let Inst{21-23} = CR;
776 let Inst{24-25} = BIBO{6-5};
777 let Inst{26-30} = xo;
778 let Inst{31} = 0;
758779 }
759780
760781 // 1.7.13 M-Form
445445 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
446446
447447 let Defs = [CTR], Uses = [CTR] in {
448 def BDZ : IForm_ext<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
449 "bdz $dst", BrB, []>;
450 def BDNZ : IForm_ext<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
451 "bdnz $dst", BrB, []>;
448 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
449 "bdz $dst">;
450 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
451 "bdnz $dst">;
452452 }
453453 }
454454
731731 []>, RegConstraint<"$addr.offreg = $ea_result">,
732732 NoEncode<"$ea_result">;
733733
734 def LHZUX : XForm_1<31, 331, (outs GPRC:$rD, ptr_rc:$ea_result),
734 def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc:$ea_result),
735735 (ins memrr:$addr),
736736 "lhzux $rD, $addr", LdStLoadUpd,
737737 []>, RegConstraint<"$addr.offreg = $ea_result">,
13941394 "fdivs $FRT, $FRA, $FRB", FPDivS,
13951395 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
13961396 def FMUL : AForm_3<63, 25,
1397 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1398 "fmul $FRT, $FRA, $FRB", FPFused,
1399 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1397 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC),
1398 "fmul $FRT, $FRA, $FRC", FPFused,
1399 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRC))]>;
14001400 def FMULS : AForm_3<59, 25,
1401 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1402 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1403 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1401 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC),
1402 "fmuls $FRT, $FRA, $FRC", FPGeneral,
1403 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRC))]>;
14041404 def FSUB : AForm_2<63, 20,
14051405 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
14061406 "fsub $FRT, $FRA, $FRB", FPAddSub,
14131413 }
14141414
14151415 let PPC970_Unit = 1 in { // FXU Operations.
1416 def ISEL : AForm_1<31, 15,
1416 def ISEL : AForm_4<31, 15,
14171417 (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB, pred:$cond),
14181418 "isel $rT, $rA, $rB, $cond", IntGeneral,
14191419 []>;
0 ;; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -filetype=obj %s -o - | \
1 ;; RUN: elf-dump --dump-section-data | FileCheck %s
2
3 ;; FIXME: this file should be in .s form, change when asm parser is available.
4
5 @t = thread_local global i32 0, align 4
6
7 define i32* @f() nounwind {
8 entry:
9 ret i32* @t
10 }
11
12 ;; Check for a pair of R_PPC64_TPREL16_HA / R_PPC64_TPREL16_LO relocs
13 ;; against the thread-local symbol 't'.
14 ;; CHECK: '.rela.text'
15 ;; CHECK: Relocation 0
16 ;; CHECK-NEXT: 'r_offset',
17 ;; CHECK-NEXT: 'r_sym', 0x00000008
18 ;; CHECK-NEXT: 'r_type', 0x00000048
19 ;; CHECK: Relocation 1
20 ;; CHECK-NEXT: 'r_offset',
21 ;; CHECK-NEXT: 'r_sym', 0x00000008
22 ;; CHECK-NEXT: 'r_type', 0x00000046
23
24 ;; Check that we got the correct symbol.
25 ;; CHECK: Symbol 8
26 ;; CHECK-NEXT: 't'
27