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[NFC] [Power] Fix instruction format for xsrqpi xsrqpi is currently using Z23Form_1. The instruction format is xsrqpi R,VRT,VRB,RMC. Rathar than bits 11-15 being used for FRA, it should have bits 11-14 reserved and bit 15 for R. This patch adds a new class Z23Form_4 to fix the instruction format. Differential Revision: https://reviews.llvm.org/D46761 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332253 91177308-0d34-0410-b5e6-96231b3b80d8 Zaara Syeda 1 year, 5 months ago
2 changed file(s) with 22 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
21302130 let Inst{31} = RC;
21312131 }
21322132
2133 class Z23Form_8 opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
2134 InstrItinClass itin, list pattern>
2135 : I {
2136 bits<5> VRT;
2137 bit R;
2138 bits<5> VRB;
2139 bits<2> idx;
2140
2141 let Pattern = pattern;
2142
2143 bit RC = 0; // set by isDOT
2144
2145 let Inst{6-10} = VRT;
2146 let Inst{11-14} = 0;
2147 let Inst{15} = R;
2148 let Inst{16-20} = VRB;
2149 let Inst{21-22} = idx;
2150 let Inst{23-30} = xo;
2151 let Inst{31} = RC;
2152 }
2153
21332154 //===----------------------------------------------------------------------===//
21342155 class Pseudo pattern>
21352156 : I<0, OOL, IOL, asmstr, NoItinerary> {
25742574
25752575 class Z23_VT5_R1_VB5_RMC2_EX1 opcode, bits<8> xo, bit ex, string opc,
25762576 list pattern>
2577 : Z23Form_1
2577 : Z23Form_8
25782578 (outs vrrc:$vT), (ins u1imm:$r, vrrc:$vB, u2imm:$rmc),
25792579 !strconcat(opc, " $r, $vT, $vB, $rmc"), IIC_VecFP, pattern> {
25802580 let RC = ex;