llvm.org GIT mirror llvm / 3b260f3
[X86] Add support to assembler and MCInst lowering to use the other vmovq %xmmX, %xmmX encoding if it would be a shorter VEX encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250014 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 5 years ago
2 changed file(s) with 28 addition(s) and 24 deletion(s). Raw diff Collapse all Expand all
23632363 bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
23642364 switch (Inst.getOpcode()) {
23652365 default: return false;
2366 case X86::VMOVZPQILo2PQIrr:
23662367 case X86::VMOVAPDrr:
23672368 case X86::VMOVAPDYrr:
23682369 case X86::VMOVAPSrr:
23822383 unsigned NewOpc;
23832384 switch (Inst.getOpcode()) {
23842385 default: llvm_unreachable("Invalid opcode");
2385 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
2386 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
2387 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
2388 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
2389 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
2390 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
2391 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
2392 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
2393 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
2394 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
2395 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
2396 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
2386 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
2387 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
2388 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
2389 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
2390 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
2391 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
2392 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
2393 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
2394 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
2395 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
2396 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
2397 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
2398 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
23972399 }
23982400 Inst.setOpcode(NewOpc);
23992401 return true;
459459
460460 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
461461 // if one of the registers is extended, but other isn't.
462 case X86::VMOVZPQILo2PQIrr:
462463 case X86::VMOVAPDrr:
463464 case X86::VMOVAPDYrr:
464465 case X86::VMOVAPSrr:
476477 unsigned NewOpc;
477478 switch (OutMI.getOpcode()) {
478479 default: llvm_unreachable("Invalid opcode");
479 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
480 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
481 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
482 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
483 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
484 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
485 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
486 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
487 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
488 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
489 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
490 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
480 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
481 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
482 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
483 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
484 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
485 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
486 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
487 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
488 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
489 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
490 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
491 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
492 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
491493 }
492494 OutMI.setOpcode(NewOpc);
493495 }