llvm.org GIT mirror llvm / 3b0887e
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).", it is failing tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146157 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Dunbar 8 years ago
2 changed file(s) with 0 addition(s) and 324 deletion(s). Raw diff Collapse all Expand all
467467
468468 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
469469 // neither Neon nor VFP support any arithmetic operations on it.
470 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
471 // supported for v4f32.
472470 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
473471 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
474472 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
475 // FIXME: Code duplication: FDIV and FREM are expanded always, see
476 // ARMTargetLowering::addTypeForNEON method for details.
477473 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
478474 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
479 // FIXME: Create unittest.
480 // In another words, find a way when "copysign" appears in DAG with vector
481 // operands.
482475 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
483 // FIXME: Code duplication: SETCC has custom operation action, see
484 // ARMTargetLowering::addTypeForNEON method for details.
485476 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
486 // FIXME: Create unittest for FNEG and for FABS.
487477 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
488478 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
489479 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
496486 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
497487 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
498488 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
499 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
500489 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
501490 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
502491 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
503492 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
504493 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
505
506 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
507 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
508 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
509 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
510 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
511 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
512 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
513 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
514 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
515 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
516494
517495 // Neon does not support some operations on v1i64 and v2i64 types.
518496 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
+0
-302
test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll less more
None ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
1
2 @A = global <4 x float>
3
4 define void @test_sqrt(<4 x float>* %X) nounwind {
5
6 ; CHECK: test_sqrt:
7
8 ; CHECK: movw r1, :lower16:A
9 ; CHECK-NEXT: movt r1, :upper16:A
10 ; CHECK: vldmia r1, {[[short0:s[0-9]+]], [[short1:s[0-9]+]], [[short2:s[0-9]+]], [[short3:s[0-9]+]]}
11 ; CHECK: vsqrt.f32 {{s[0-9]+}}, [[short3]]
12 ; CHECK: vsqrt.f32 {{s[0-9]+}}, [[short2]]
13 ; CHECK: vsqrt.f32 {{s[0-9]+}}, [[short1]]
14 ; CHECK: vsqrt.f32 {{s[0-9]+}}, [[short0]]
15 ; CHECK-NEXT: vstmia {{.*}}
16
17 L.entry:
18 %0 = load <4 x float>* @A, align 16
19 %1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
20 store <4 x float> %1, <4 x float>* %X, align 16
21 ret void
22 }
23
24 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
25
26
27 define void @test_cos(<4 x float>* %X) nounwind {
28
29 ; CHECK: test_cos:
30
31 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:A
32 ; CHECK-NEXT: movt [[reg0]], :upper16:A
33 ; CHECK: vldmia [[reg0]], {{.*}}
34
35 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
36 ; CHECK: bl cosf
37
38 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
39 ; CHECK: bl cosf
40
41 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
42 ; CHECK: bl cosf
43
44 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
45 ; CHECK: bl cosf
46
47 ; CHECK: vstmia {{.*}}
48
49 L.entry:
50 %0 = load <4 x float>* @A, align 16
51 %1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0)
52 store <4 x float> %1, <4 x float>* %X, align 16
53 ret void
54 }
55
56 declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly
57
58 define void @test_exp(<4 x float>* %X) nounwind {
59
60 ; CHECK: test_exp:
61
62 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:A
63 ; CHECK-NEXT: movt [[reg0]], :upper16:A
64 ; CHECK: vldmia [[reg0]], {{.*}}
65
66 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
67 ; CHECK: bl expf
68
69 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
70 ; CHECK: bl expf
71
72 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
73 ; CHECK: bl expf
74
75 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
76 ; CHECK: bl expf
77
78 ; CHECK: vstmia {{.*}}
79
80 L.entry:
81 %0 = load <4 x float>* @A, align 16
82 %1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0)
83 store <4 x float> %1, <4 x float>* %X, align 16
84 ret void
85 }
86
87 declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly
88
89 define void @test_exp2(<4 x float>* %X) nounwind {
90
91 ; CHECK: test_exp2:
92
93 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:A
94 ; CHECK-NEXT: movt [[reg0]], :upper16:A
95 ; CHECK: vldmia [[reg0]], {{.*}}
96
97 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
98 ; CHECK: bl exp2f
99
100 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
101 ; CHECK: bl exp2f
102
103 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
104 ; CHECK: bl exp2f
105
106 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
107 ; CHECK: bl exp2f
108
109 ; CHECK: vstmia {{.*}}
110
111 L.entry:
112 %0 = load <4 x float>* @A, align 16
113 %1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0)
114 store <4 x float> %1, <4 x float>* %X, align 16
115 ret void
116 }
117
118 declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly
119
120 define void @test_log10(<4 x float>* %X) nounwind {
121
122 ; CHECK: test_log10:
123
124 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:A
125 ; CHECK-NEXT: movt [[reg0]], :upper16:A
126 ; CHECK: vldmia [[reg0]], {{.*}}
127
128 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
129 ; CHECK: bl log10f
130
131 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
132 ; CHECK: bl log10f
133
134 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
135 ; CHECK: bl log10f
136
137 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
138 ; CHECK: bl log10f
139
140 ; CHECK: vstmia {{.*}}
141
142 L.entry:
143 %0 = load <4 x float>* @A, align 16
144 %1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0)
145 store <4 x float> %1, <4 x float>* %X, align 16
146 ret void
147 }
148
149 declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly
150
151 define void @test_log(<4 x float>* %X) nounwind {
152
153 ; CHECK: test_log:
154
155 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:A
156 ; CHECK-NEXT: movt [[reg0]], :upper16:A
157 ; CHECK: vldmia [[reg0]], {{.*}}
158
159 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
160 ; CHECK: bl logf
161
162 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
163 ; CHECK: bl logf
164
165 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
166 ; CHECK: bl logf
167
168 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
169 ; CHECK: bl logf
170
171 ; CHECK: vstmia {{.*}}
172
173 L.entry:
174 %0 = load <4 x float>* @A, align 16
175 %1 = call <4 x float> @llvm.log.v4f32(<4 x float> %0)
176 store <4 x float> %1, <4 x float>* %X, align 16
177 ret void
178 }
179
180 declare <4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly
181
182 define void @test_log2(<4 x float>* %X) nounwind {
183
184 ; CHECK: test_log2:
185
186 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:A
187 ; CHECK-NEXT: movt [[reg0]], :upper16:A
188 ; CHECK: vldmia [[reg0]], {{.*}}
189
190 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
191 ; CHECK: bl log2f
192
193 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
194 ; CHECK: bl log2f
195
196 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
197 ; CHECK: bl log2f
198
199 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
200 ; CHECK: bl log2f
201
202 ; CHECK: vstmia {{.*}}
203
204 L.entry:
205 %0 = load <4 x float>* @A, align 16
206 %1 = call <4 x float> @llvm.log2.v4f32(<4 x float> %0)
207 store <4 x float> %1, <4 x float>* %X, align 16
208 ret void
209 }
210
211 declare <4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly
212
213
214 define void @test_pow(<4 x float>* %X) nounwind {
215
216 ; CHECK: test_pow:
217
218 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:A
219 ; CHECK-NEXT: movt [[reg0]], :upper16:A
220 ; CHECK: vldmia [[reg0]], {{.*}}
221
222 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
223 ; CHECK: bl powf
224
225 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
226 ; CHECK: bl powf
227
228 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
229 ; CHECK: bl powf
230
231 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
232 ; CHECK: bl powf
233
234 ; CHECK: vstmia {{.*}}
235
236 L.entry:
237
238 %0 = load <4 x float>* @A, align 16
239 %1 = call <4 x float> @llvm.pow.v4f32(<4 x float> %0, <4 x float> )
240
241 store <4 x float> %1, <4 x float>* %X, align 16
242
243 ret void
244 }
245
246 declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) nounwind readonly
247
248 define void @test_powi(<4 x float>* %X) nounwind {
249
250 ; CHECK: test_powi:
251
252 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:A
253 ; CHECK-NEXT: movt [[reg0]], :upper16:A
254 ; CHECK-NEXT: vldmia [[reg0]], {{.*}}
255 ; CHECK: vmul.f32 {{.*}}
256
257 ; CHECK: vstmia {{.*}}
258
259 L.entry:
260
261 %0 = load <4 x float>* @A, align 16
262 %1 = call <4 x float> @llvm.powi.v4f32(<4 x float> %0, i32 2)
263
264 store <4 x float> %1, <4 x float>* %X, align 16
265
266 ret void
267 }
268
269 declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly
270
271 define void @test_sin(<4 x float>* %X) nounwind {
272
273 ; CHECK: test_sin:
274
275 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:A
276 ; CHECK-NEXT: movt [[reg0]], :upper16:A
277 ; CHECK: vldmia [[reg0]], {{.*}}
278
279 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
280 ; CHECK: bl sinf
281
282 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
283 ; CHECK: bl sinf
284
285 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
286 ; CHECK: bl sinf
287
288 ; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
289 ; CHECK: bl sinf
290
291 ; CHECK: vstmia {{.*}}
292
293 L.entry:
294 %0 = load <4 x float>* @A, align 16
295 %1 = call <4 x float> @llvm.sin.v4f32(<4 x float> %0)
296 store <4 x float> %1, <4 x float>* %X, align 16
297 ret void
298 }
299
300 declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly
301