llvm.org GIT mirror llvm / 3ae900a
In LLVM 2.9, the GHC calling convention is only supported on x86-32, x86-64. We (GHC team) would like this patch included as we've recently added support to GHC for the ARM platform. Patch by David Terei! git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142820 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 7 years ago
5 changed file(s) with 50 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
6262
6363 const unsigned*
6464 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
65 bool ghcCall = false;
66
67 if (MF) {
68 const Function *F = MF->getFunction();
69 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
70 }
71
6572 static const unsigned CalleeSavedRegs[] = {
6673 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
6774 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
8188 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
8289 0
8390 };
84 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
91
92 static const unsigned GhcCalleeSavedRegs[] = {
93 0
94 };
95
96 return ghcCall ? GhcCalleeSavedRegs :
97 STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
8598 }
8699
87100 BitVector ARMBaseRegisterInfo::
8181 CCDelegateTo
8282 ]>;
8383
84 //===----------------------------------------------------------------------===//
85 // ARM APCS Calling Convention for GHC
86 //===----------------------------------------------------------------------===//
87
88 def CC_ARM_APCS_GHC : CallingConv<[
89 // Handle all vector types as either f64 or v2f64.
90 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>,
91 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType>,
92
93 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
94 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
95 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
96
97 // Promote i8/i16 arguments to i32.
98 CCIfType<[i8, i16], CCPromoteToType>,
99
100 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
101 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
102 ]>;
84103
85104 //===----------------------------------------------------------------------===//
86105 // ARM AAPCS (EABI) Calling Convention, common parts
15471547 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
15481548 case CallingConv::ARM_APCS:
15491549 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1550 case CallingConv::GHC:
1551 if (Return)
1552 llvm_unreachable("Can't return in GHC call convention");
1553 else
1554 return CC_ARM_APCS_GHC;
15501555 }
15511556 }
15521557
1414 #include "ARMBaseInstrInfo.h"
1515 #include "ARMBaseRegisterInfo.h"
1616 #include "ARMMachineFunctionInfo.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Function.h"
1719 #include "MCTargetDesc/ARMAddressingModes.h"
1820 #include "llvm/CodeGen/MachineFrameInfo.h"
1921 #include "llvm/CodeGen/MachineFunction.h"
137139 // belongs to which callee-save spill areas.
138140 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
139141 int FramePtrSpillFI = 0;
142
143 // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue.
144 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
145 return;
140146
141147 // Allocate the vararg register save area. This is not counted in NumBytes.
142148 if (VARegSaveSize)
324330 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
325331 int NumBytes = (int)MFI->getStackSize();
326332 unsigned FramePtr = RegInfo->getFrameRegister(MF);
333
334 // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue.
335 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
336 return;
327337
328338 if (!AFI->hasStackFrame()) {
329339 if (NumBytes != 0)
10901090 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
10911091 case CallingConv::ARM_APCS:
10921092 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1093 case CallingConv::GHC:
1094 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
10931095 }
10941096 }
10951097