llvm.org GIT mirror llvm / 3ad5e5c
add shifts to addressing mode 1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30291 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 13 years ago
6 changed file(s) with 84 addition(s) and 35 deletion(s). Raw diff Collapse all Expand all
4040 };
4141 }
4242
43 namespace ARMShift {
44 enum ShiftTypes {
45 LSL,
46 LSR,
47 ASR,
48 ROR,
49 RRX
50 };
51 }
52
4353 static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
4454 switch (CC) {
4555 default: assert(0 && "Unknown condition code");
157157 }
158158
159159 void ARMAsmPrinter::printAddrMode1(const MachineInstr *MI, int opNum) {
160 const MachineOperand &MO1 = MI->getOperand(opNum);
161
162 if(MO1.isImmediate()) {
160 const MachineOperand &Arg = MI->getOperand(opNum);
161 const MachineOperand &Shift = MI->getOperand(opNum + 1);
162 const MachineOperand &ShiftType = MI->getOperand(opNum + 2);
163
164 if(Arg.isImmediate()) {
165 assert(Shift.getImmedValue() == 0);
163166 printOperand(MI, opNum);
164167 } else {
165 assert(MO1.isRegister());
168 assert(Arg.isRegister());
166169 printOperand(MI, opNum);
170 if(Shift.isRegister() || Shift.getImmedValue() != 0) {
171 const char *s = NULL;
172 switch(ShiftType.getImmedValue()) {
173 case ARMShift::LSL:
174 s = ", lsl ";
175 break;
176 case ARMShift::LSR:
177 s = ", lsr ";
178 break;
179 case ARMShift::ASR:
180 s = ", asr ";
181 break;
182 case ARMShift::ROR:
183 s = ", ror ";
184 break;
185 case ARMShift::RRX:
186 s = ", rrx ";
187 break;
188 }
189 O << s;
190 printOperand(MI, opNum + 1);
191 }
167192 }
168193 }
169194
444444 SDNode *Select(SDOperand Op);
445445 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
446446 bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
447 bool SelectAddrMode1(SDOperand N, SDOperand &Arg);
447 bool SelectAddrMode1(SDOperand N, SDOperand &Arg, SDOperand &Shift,
448 SDOperand &ShiftType);
448449
449450 // Include the pieces autogenerated from the target description.
450451 #include "ARMGenDAGISel.inc"
479480 }
480481
481482 bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
482 SDOperand &Arg) {
483 SDOperand &Arg,
484 SDOperand &Shift,
485 SDOperand &ShiftType) {
483486 switch(N.getOpcode()) {
484487 case ISD::Constant: {
485488 //TODO:check that we have a valid constant
486489 int32_t t = cast(N)->getValue();
487 Arg = CurDAG->getTargetConstant(t, MVT::i32);
490 Arg = CurDAG->getTargetConstant(t, MVT::i32);
491 Shift = CurDAG->getTargetConstant(0, MVT::i32);
492 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
488493 return true;
489494 }
490 }
491
492 Arg = N;
495 case ISD::SRA:
496 Arg = N.getOperand(0);
497 Shift = N.getOperand(1);
498 ShiftType = CurDAG->getTargetConstant(ARMShift::ASR, MVT::i32);
499 return true;
500 case ISD::SRL:
501 Arg = N.getOperand(0);
502 Shift = N.getOperand(1);
503 ShiftType = CurDAG->getTargetConstant(ARMShift::LSR, MVT::i32);
504 return true;
505 case ISD::SHL:
506 Arg = N.getOperand(0);
507 Shift = N.getOperand(1);
508 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
509 return true;
510 }
511
512 Arg = N;
513 Shift = CurDAG->getTargetConstant(0, MVT::i32);
514 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
493515 return true;
494516 }
495517
3232 unsigned &SrcReg, unsigned &DstReg) const {
3333 MachineOpCode oc = MI.getOpcode();
3434 switch (oc) {
35 case ARM::MOV:
36 assert(MI.getNumOperands() == 2 &&
35 case ARM::MOV: {
36 assert(MI.getNumOperands() == 4 &&
3737 MI.getOperand(0).isRegister() &&
3838 "Invalid ARM MOV instruction");
39 if (MI.getOperand(1).isRegister()) {
39 const MachineOperand &Arg = MI.getOperand(1);
40 const MachineOperand &Shift = MI.getOperand(2);
41 if (Arg.isRegister() && Shift.isImmediate() && Shift.getImmedValue() == 0) {
4042 SrcReg = MI.getOperand(1).getReg();
4143 DstReg = MI.getOperand(0).getReg();
4244 return true;
4345 }
4446 }
47 }
4548 return false;
4649 }
1414 // Address operands
1515 def op_addr_mode1 : Operand {
1616 let PrintMethod = "printAddrMode1";
17 let NumMIOperands = 1;
18 let MIOperandInfo = (ops ptr_rc);
17 let NumMIOperands = 3;
18 let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
1919 }
2020
2121 def memri : Operand {
2626
2727 // Define ARM specific addressing mode.
2828 //Addressing Mode 1: data processing operands
29 def addr_mode1 : ComplexPattern1, "SelectAddrMode1", [imm]>;
29 def addr_mode1 : ComplexPattern3, "SelectAddrMode1", [imm, sra, shl, srl]>;
3030
3131 //register plus/minus 12 bit offset
3232 def iaddr : ComplexPattern;
118118 "and $dst, $a, $b",
119119 [(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
120120
121 // All arm data processing instructions have a shift. Maybe we don't have
122 // to implement this
123 def SHL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
124 "mov $dst, $a, lsl $b",
125 [(set IntRegs:$dst, (shl IntRegs:$a, IntRegs:$b))]>;
126
127 def SRA : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
128 "mov $dst, $a, asr $b",
129 [(set IntRegs:$dst, (sra IntRegs:$a, IntRegs:$b))]>;
130
131 def SRL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
132 "mov $dst, $a, lsr $b",
133 [(set IntRegs:$dst, (srl IntRegs:$a, IntRegs:$b))]>;
134
135
136121 def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
137122 "eor $dst, $a, $b",
138123 [(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
4747 unsigned DestReg, unsigned SrcReg,
4848 const TargetRegisterClass *RC) const {
4949 assert (RC == ARM::IntRegsRegisterClass);
50 BuildMI(MBB, I, ARM::MOV, 1, DestReg).addReg(SrcReg);
50 BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
51 .addImm(ARMShift::LSL);
5152 }
5253
5354 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
113114 // Insert a set of r12 with the full address
114115 // r12 = r13 + offset
115116 MachineBasicBlock *MBB2 = MI.getParent();
116 BuildMI(*MBB2, II, ARM::ADD, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
117 BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(ARM::R13).addImm(Offset)
118 .addImm(0).addImm(ARMShift::LSL);
117119
118120 // Replace the FrameIndex with r12
119121 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
139141 MFI->setStackSize(NumBytes);
140142
141143 //sub sp, sp, #NumBytes
142 BuildMI(MBB, MBBI, ARM::SUB, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
144 BuildMI(MBB, MBBI, ARM::SUB, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
145 .addImm(0).addImm(ARMShift::LSL);
143146 }
144147
145148 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
152155 int NumBytes = (int) MFI->getStackSize();
153156
154157 //add sp, sp, #NumBytes
155 BuildMI(MBB, MBBI, ARM::ADD, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
158 BuildMI(MBB, MBBI, ARM::ADD, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
159 .addImm(0).addImm(ARMShift::LSL);
156160 }
157161
158162 unsigned ARMRegisterInfo::getRARegister() const {