llvm.org GIT mirror llvm / 3ac1884
split the vector case of getCopyFromParts out to its own function, no functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111994 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 10 years ago
1 changed file(s) with 104 addition(s) and 83 deletion(s). Raw diff Collapse all Expand all
6969 cl::location(LimitFloatPrecision),
7070 cl::init(0));
7171
72 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
73 const SDValue *Parts, unsigned NumParts,
74 EVT PartVT, EVT ValueVT);
75
7276 /// getCopyFromParts - Create a value that contains the specified legal parts
7377 /// combined into the value they represent. If the parts combine to a type
7478 /// larger then ValueVT then AssertOp can be used to specify whether the extra
7579 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
7680 /// (ISD::AssertSext).
77 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
81 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
7882 const SDValue *Parts,
7983 unsigned NumParts, EVT PartVT, EVT ValueVT,
8084 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
85 if (ValueVT.isVector())
86 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
87
8188 assert(NumParts > 0 && "No parts to assemble!");
8289 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8390 SDValue Val = Parts[0];
8491
8592 if (NumParts > 1) {
8693 // Assemble the value from multiple parts.
87 if (!ValueVT.isVector() && ValueVT.isInteger()) {
94 if (ValueVT.isInteger()) {
8895 unsigned PartBits = PartVT.getSizeInBits();
8996 unsigned ValueBits = ValueVT.getSizeInBits();
9097
99106 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
100107
101108 if (RoundParts > 2) {
102 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts / 2,
109 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
103110 PartVT, HalfVT);
104 Hi = getCopyFromParts(DAG, dl, Parts + RoundParts / 2,
111 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
105112 RoundParts / 2, PartVT, HalfVT);
106113 } else {
107 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
108 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
114 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[0]);
115 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[1]);
109116 }
110117
111118 if (TLI.isBigEndian())
112119 std::swap(Lo, Hi);
113120
114 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
121 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
115122
116123 if (RoundParts < NumParts) {
117124 // Assemble the trailing non-power-of-2 part.
118125 unsigned OddParts = NumParts - RoundParts;
119126 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
120 Hi = getCopyFromParts(DAG, dl,
127 Hi = getCopyFromParts(DAG, DL,
121128 Parts + RoundParts, OddParts, PartVT, OddVT);
122129
123130 // Combine the round and odd parts.
125132 if (TLI.isBigEndian())
126133 std::swap(Lo, Hi);
127134 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
128 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
129 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
135 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
136 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
130137 DAG.getConstant(Lo.getValueType().getSizeInBits(),
131138 TLI.getPointerTy()));
132 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
133 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
139 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
140 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
134141 }
135 } else if (ValueVT.isVector()) {
136 // Handle a multi-element vector.
137 EVT IntermediateVT, RegisterVT;
138 unsigned NumIntermediates;
139 unsigned NumRegs =
140 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
141 NumIntermediates, RegisterVT);
142 assert(NumRegs == NumParts
143 && "Part count doesn't match vector breakdown!");
144 NumParts = NumRegs; // Silence a compiler warning.
145 assert(RegisterVT == PartVT
146 && "Part type doesn't match vector breakdown!");
147 assert(RegisterVT == Parts[0].getValueType() &&
148 "Part type doesn't match part!");
149
150 // Assemble the parts into intermediate operands.
151 SmallVector Ops(NumIntermediates);
152 if (NumIntermediates == NumParts) {
153 // If the register was not expanded, truncate or copy the value,
154 // as appropriate.
155 for (unsigned i = 0; i != NumParts; ++i)
156 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
157 PartVT, IntermediateVT);
158 } else if (NumParts > 0) {
159 // If the intermediate type was expanded, build the intermediate
160 // operands from the parts.
161 assert(NumParts % NumIntermediates == 0 &&
162 "Must expand into a divisible number of parts!");
163 unsigned Factor = NumParts / NumIntermediates;
164 for (unsigned i = 0; i != NumIntermediates; ++i)
165 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
166 PartVT, IntermediateVT);
167 }
168
169 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
170 // intermediate operands.
171 Val = DAG.getNode(IntermediateVT.isVector() ?
172 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
173 ValueVT, &Ops[0], NumIntermediates);
174142 } else if (PartVT.isFloatingPoint()) {
175143 // FP split into multiple FP parts (for ppcf128)
176144 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
177145 "Unexpected split");
178146 SDValue Lo, Hi;
179 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
180 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
147 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[0]);
148 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[1]);
181149 if (TLI.isBigEndian())
182150 std::swap(Lo, Hi);
183 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
151 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
184152 } else {
185153 // FP split into integer parts (soft fp)
186154 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
187155 !PartVT.isVector() && "Unexpected split");
188156 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
189 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
157 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
190158 }
191159 }
192160
196164 if (PartVT == ValueVT)
197165 return Val;
198166
199 if (PartVT.isVector()) {
200 assert(ValueVT.isVector() && "Unknown vector conversion!");
201 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
202 }
203
204 if (ValueVT.isVector()) {
205 assert(ValueVT.getVectorElementType() == PartVT &&
206 ValueVT.getVectorNumElements() == 1 &&
207 "Only trivial scalar-to-vector conversions should get here!");
208 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
209 }
210
211 if (PartVT.isInteger() &&
212 ValueVT.isInteger()) {
167 if (PartVT.isInteger() && ValueVT.isInteger()) {
213168 if (ValueVT.bitsLT(PartVT)) {
214169 // For a truncate, see if we have any information to
215170 // indicate whether the truncated bits will always be
216171 // zero or sign-extension.
217172 if (AssertOp != ISD::DELETED_NODE)
218 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
173 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
219174 DAG.getValueType(ValueVT));
220 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
221 } else {
222 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
223 }
175 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
176 }
177 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
224178 }
225179
226180 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
227 if (ValueVT.bitsLT(Val.getValueType())) {
228 // FP_ROUND's are always exact here.
229 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
181 // FP_ROUND's are always exact here.
182 if (ValueVT.bitsLT(Val.getValueType()))
183 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
230184 DAG.getIntPtrConstant(1));
231 }
232
233 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
185
186 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
234187 }
235188
236189 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
237 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
190 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val);
238191
239192 llvm_unreachable("Unknown mismatch!");
240193 return SDValue();
241194 }
195
196 /// getCopyFromParts - Create a value that contains the specified legal parts
197 /// combined into the value they represent. If the parts combine to a type
198 /// larger then ValueVT then AssertOp can be used to specify whether the extra
199 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
200 /// (ISD::AssertSext).
201 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
202 const SDValue *Parts, unsigned NumParts,
203 EVT PartVT, EVT ValueVT) {
204 assert(ValueVT.isVector() && "Not a vector value");
205 assert(NumParts > 0 && "No parts to assemble!");
206 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
207 SDValue Val = Parts[0];
208
209 // Handle a multi-element vector.
210 if (NumParts > 1) {
211 EVT IntermediateVT, RegisterVT;
212 unsigned NumIntermediates;
213 unsigned NumRegs =
214 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
215 NumIntermediates, RegisterVT);
216 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
217 NumParts = NumRegs; // Silence a compiler warning.
218 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
219 assert(RegisterVT == Parts[0].getValueType() &&
220 "Part type doesn't match part!");
221
222 // Assemble the parts into intermediate operands.
223 SmallVector Ops(NumIntermediates);
224 if (NumIntermediates == NumParts) {
225 // If the register was not expanded, truncate or copy the value,
226 // as appropriate.
227 for (unsigned i = 0; i != NumParts; ++i)
228 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
229 PartVT, IntermediateVT);
230 } else if (NumParts > 0) {
231 // If the intermediate type was expanded, build the intermediate
232 // operands from the parts.
233 assert(NumParts % NumIntermediates == 0 &&
234 "Must expand into a divisible number of parts!");
235 unsigned Factor = NumParts / NumIntermediates;
236 for (unsigned i = 0; i != NumIntermediates; ++i)
237 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
238 PartVT, IntermediateVT);
239 }
240
241 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
242 // intermediate operands.
243 Val = DAG.getNode(IntermediateVT.isVector() ?
244 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
245 ValueVT, &Ops[0], NumIntermediates);
246 }
247
248 // There is now one part, held in Val. Correct it to match ValueVT.
249 PartVT = Val.getValueType();
250
251 if (PartVT == ValueVT)
252 return Val;
253
254 if (PartVT.isVector()) // Vector/Vector bitcast.
255 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val);
256
257 assert(ValueVT.getVectorElementType() == PartVT &&
258 ValueVT.getVectorNumElements() == 1 &&
259 "Only trivial scalar-to-vector conversions should get here!");
260 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
261 }
262
263
242264
243265
244266 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
635657 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
636658 EVT RegisterVT = RegVTs[Value];
637659
638 getCopyToParts(DAG, dl,
639 Val.getValue(Val.getResNo() + Value),
660 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
640661 &Parts[Part], NumParts, RegisterVT);
641662 Part += NumParts;
642663 }