llvm.org GIT mirror llvm / 3abd23b
R600: Reorganize lit tests and document how they should be organized git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179828 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 6 years ago
40 changed file(s) with 394 addition(s) and 348 deletion(s). Raw diff Collapse all Expand all
0 +==============================================================================+
1 | How to organize the lit tests |
2 +==============================================================================+
3
4 - If you write a test for matching a single DAG opcode or intrinsic, it should
5 go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)
6
7 - If you write a test that matches several DAG opcodes and checks for a single
8 ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
9 bfi_int.ll
10
11 - For all other tests, use your best judgement for organizing tests and naming
12 the files.
13
14 +==============================================================================+
15 | Naming conventions |
16 +==============================================================================+
17
18 - Use dash '-' and not underscore '_' to separate words in file names, unless
19 the file is named after a DAG opcode or ISA instruction that has an
20 underscore '_' in its name.
0 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3 ;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6
7 define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
8 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
9 %a = load <4 x i32> addrspace(1) * %in
10 %b = load <4 x i32> addrspace(1) * %b_ptr
11 %result = add <4 x i32> %a, %b
12 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
13 ret void
14 }
+0
-15
test/CodeGen/R600/add.v4i32.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3 ;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6
7 define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
8 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
9 %a = load <4 x i32> addrspace(1) * %in
10 %b = load <4 x i32> addrspace(1) * %b_ptr
11 %result = add <4 x i32> %a, %b
12 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
13 ret void
14 }
0 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3 ;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6
7 define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
8 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
9 %a = load <4 x i32> addrspace(1) * %in
10 %b = load <4 x i32> addrspace(1) * %b_ptr
11 %result = and <4 x i32> %a, %b
12 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
13 ret void
14 }
+0
-15
test/CodeGen/R600/and.v4i32.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3 ;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6
7 define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
8 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
9 %a = load <4 x i32> addrspace(1) * %in
10 %b = load <4 x i32> addrspace(1) * %b_ptr
11 %result = and <4 x i32> %a, %b
12 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
13 ret void
14 }
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
11
2 ; CHECK: @fadd_f32
23 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
34
4 define void @test() {
5 define void @fadd_f32() {
56 %r0 = call float @llvm.R600.load.input(i32 0)
67 %r1 = call float @llvm.R600.load.input(i32 1)
78 %r2 = fadd float %r0, %r1
1314
1415 declare void @llvm.AMDGPU.store.output(float, i32)
1516
17 ; CHECK: @fadd_v4f32
18 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
19 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
20 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
21 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
22
23 define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
24 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
25 %a = load <4 x float> addrspace(1) * %in
26 %b = load <4 x float> addrspace(1) * %b_ptr
27 %result = fadd <4 x float> %a, %b
28 store <4 x float> %result, <4 x float> addrspace(1)* %out
29 ret void
30 }
+0
-15
test/CodeGen/R600/fadd.v4f32.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3 ;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6
7 define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
8 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
9 %a = load <4 x float> addrspace(1) * %in
10 %b = load <4 x float> addrspace(1) * %b_ptr
11 %result = fadd <4 x float> %a, %b
12 store <4 x float> %result, <4 x float> addrspace(1)* %out
13 ret void
14 }
0 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3 ;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6 ;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
7 ;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
8 ;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
9 ;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
10
11 define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
12 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
13 %a = load <4 x float> addrspace(1) * %in
14 %b = load <4 x float> addrspace(1) * %b_ptr
15 %result = fdiv <4 x float> %a, %b
16 store <4 x float> %result, <4 x float> addrspace(1)* %out
17 ret void
18 }
+0
-19
test/CodeGen/R600/fdiv.v4f32.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3 ;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6 ;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
7 ;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
8 ;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
9 ;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
10
11 define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
12 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
13 %a = load <4 x float> addrspace(1) * %in
14 %b = load <4 x float> addrspace(1) * %b_ptr
15 %result = fdiv <4 x float> %a, %b
16 store <4 x float> %result, <4 x float> addrspace(1)* %out
17 ret void
18 }
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
11
2 ; CHECK: @fmul_f32
23 ; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
34
4 define void @test() {
5 define void @fmul_f32() {
56 %r0 = call float @llvm.R600.load.input(i32 0)
67 %r1 = call float @llvm.R600.load.input(i32 1)
78 %r2 = fmul float %r0, %r1
1314
1415 declare void @llvm.AMDGPU.store.output(float, i32)
1516
17 ; CHECK: @fmul_v4f32
18 ; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
19 ; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
20 ; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
21 ; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
22
23 define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
24 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
25 %a = load <4 x float> addrspace(1) * %in
26 %b = load <4 x float> addrspace(1) * %b_ptr
27 %result = fmul <4 x float> %a, %b
28 store <4 x float> %result, <4 x float> addrspace(1)* %out
29 ret void
30 }
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ; CHECK: @fp_to_sint_v4i32
3 ; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6 ; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
7
8 define void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
9 %value = load <4 x float> addrspace(1) * %in
10 %result = fptosi <4 x float> %value to <4 x i32>
11 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
12 ret void
13 }
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ; CHECK: @fp_to_uint_v4i32
3 ; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6 ; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
7
8 define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
9 %value = load <4 x float> addrspace(1) * %in
10 %result = fptoui <4 x float> %value to <4 x i32>
11 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
12 ret void
13 }
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
11
2 ; CHECK: @fsub_f32
23 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
34
4 define void @test() {
5 define void @fsub_f32() {
56 %r0 = call float @llvm.R600.load.input(i32 0)
67 %r1 = call float @llvm.R600.load.input(i32 1)
78 %r2 = fsub float %r0, %r1
1314
1415 declare void @llvm.AMDGPU.store.output(float, i32)
1516
17 ; CHECK: @fsub_v4f32
18 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
19 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
20 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
21 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
22
23 define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
24 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
25 %a = load <4 x float> addrspace(1) * %in
26 %b = load <4 x float> addrspace(1) * %b_ptr
27 %result = fsub <4 x float> %a, %b
28 store <4 x float> %result, <4 x float> addrspace(1)* %out
29 ret void
30 }
+0
-15
test/CodeGen/R600/fsub.v4f32.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3 ;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6
7 define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
8 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
9 %a = load <4 x float> addrspace(1) * %in
10 %b = load <4 x float> addrspace(1) * %b_ptr
11 %result = fsub <4 x float> %a, %b
12 store <4 x float> %result, <4 x float> addrspace(1)* %out
13 ret void
14 }
0 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3
4 define void @test(float addrspace(1)* %out, i8 addrspace(1)* %in) {
5 %1 = load i8 addrspace(1)* %in
6 %2 = uitofp i8 %1 to double
7 %3 = fptrunc double %2 to float
8 store float %3, float addrspace(1)* %out
9 ret void
10 }
+0
-11
test/CodeGen/R600/i8_to_double_to_float.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
3
4 define void @test(float addrspace(1)* %out, i8 addrspace(1)* %in) {
5 %1 = load i8 addrspace(1)* %in
6 %2 = uitofp i8 %1 to double
7 %3 = fptrunc double %2 to float
8 store float %3, float addrspace(1)* %out
9 ret void
10 }
0 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ; CHECK: JUMP @3
3 ; CHECK: EXPORT
4 ; CHECK-NOT: EXPORT
5
6 define void @main() #0 {
7 main_body:
8 %0 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
9 %1 = extractelement <4 x float> %0, i32 0
10 %2 = bitcast float %1 to i32
11 %3 = icmp eq i32 %2, 0
12 %4 = sext i1 %3 to i32
13 %5 = bitcast i32 %4 to float
14 %6 = bitcast float %5 to i32
15 %7 = icmp ne i32 %6, 0
16 br i1 %7, label %ENDIF, label %ELSE
17
18 ELSE: ; preds = %main_body
19 %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
20 %9 = extractelement <4 x float> %8, i32 0
21 %10 = bitcast float %9 to i32
22 %11 = icmp eq i32 %10, 1
23 %12 = sext i1 %11 to i32
24 %13 = bitcast i32 %12 to float
25 %14 = bitcast float %13 to i32
26 %15 = icmp ne i32 %14, 0
27 br i1 %15, label %IF13, label %ENDIF
28
29 ENDIF: ; preds = %IF13, %ELSE, %main_body
30 %temp.0 = phi float [ 0xFFF8000000000000, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
31 %temp1.0 = phi float [ 0.000000e+00, %main_body ], [ %23, %IF13 ], [ 0.000000e+00, %ELSE ]
32 %temp2.0 = phi float [ 1.000000e+00, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
33 %temp3.0 = phi float [ 5.000000e-01, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
34 %16 = insertelement <4 x float> undef, float %temp.0, i32 0
35 %17 = insertelement <4 x float> %16, float %temp1.0, i32 1
36 %18 = insertelement <4 x float> %17, float %temp2.0, i32 2
37 %19 = insertelement <4 x float> %18, float %temp3.0, i32 3
38 call void @llvm.R600.store.swizzle(<4 x float> %19, i32 0, i32 0)
39 ret void
40
41 IF13: ; preds = %ELSE
42 %20 = load <4 x float> addrspace(8)* null
43 %21 = extractelement <4 x float> %20, i32 0
44 %22 = fsub float -0.000000e+00, %21
45 %23 = fadd float 0xFFF8000000000000, %22
46 br label %ENDIF
47 }
48
49 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
50
51 attributes #0 = { "ShaderType"="0" }
+0
-52
test/CodeGen/R600/jump_address.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ; CHECK: JUMP @3
3 ; CHECK: EXPORT
4 ; CHECK-NOT: EXPORT
5
6 define void @main() #0 {
7 main_body:
8 %0 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
9 %1 = extractelement <4 x float> %0, i32 0
10 %2 = bitcast float %1 to i32
11 %3 = icmp eq i32 %2, 0
12 %4 = sext i1 %3 to i32
13 %5 = bitcast i32 %4 to float
14 %6 = bitcast float %5 to i32
15 %7 = icmp ne i32 %6, 0
16 br i1 %7, label %ENDIF, label %ELSE
17
18 ELSE: ; preds = %main_body
19 %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
20 %9 = extractelement <4 x float> %8, i32 0
21 %10 = bitcast float %9 to i32
22 %11 = icmp eq i32 %10, 1
23 %12 = sext i1 %11 to i32
24 %13 = bitcast i32 %12 to float
25 %14 = bitcast float %13 to i32
26 %15 = icmp ne i32 %14, 0
27 br i1 %15, label %IF13, label %ENDIF
28
29 ENDIF: ; preds = %IF13, %ELSE, %main_body
30 %temp.0 = phi float [ 0xFFF8000000000000, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
31 %temp1.0 = phi float [ 0.000000e+00, %main_body ], [ %23, %IF13 ], [ 0.000000e+00, %ELSE ]
32 %temp2.0 = phi float [ 1.000000e+00, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
33 %temp3.0 = phi float [ 5.000000e-01, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
34 %16 = insertelement <4 x float> undef, float %temp.0, i32 0
35 %17 = insertelement <4 x float> %16, float %temp1.0, i32 1
36 %18 = insertelement <4 x float> %17, float %temp2.0, i32 2
37 %19 = insertelement <4 x float> %18, float %temp3.0, i32 3
38 call void @llvm.R600.store.swizzle(<4 x float> %19, i32 0, i32 0)
39 ret void
40
41 IF13: ; preds = %ELSE
42 %20 = load <4 x float> addrspace(8)* null
43 %21 = extractelement <4 x float> %20, i32 0
44 %22 = fsub float -0.000000e+00, %21
45 %23 = fadd float 0xFFF8000000000000, %22
46 br label %ENDIF
47 }
48
49 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
50
51 attributes #0 = { "ShaderType"="0" }
+0
-9
test/CodeGen/R600/load.constant_addrspace.f32.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: VTX_READ_32 T{{[0-9]+\.X, T[0-9]+\.X}}
3
4 define void @test(float addrspace(1)* %out, float addrspace(2)* %in) {
5 %1 = load float addrspace(2)* %in
6 store float %1, float addrspace(1)* %out
7 ret void
8 }
+0
-10
test/CodeGen/R600/load.i8.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
3
4 define void @test(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
5 %1 = load i8 addrspace(1)* %in
6 %2 = zext i8 %1 to i32
7 store i32 %2, i32 addrspace(1)* %out
8 ret void
9 }
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ; Load an i8 value from the global address space.
3 ; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
4
5 define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
6 %1 = load i8 addrspace(1)* %in
7 %2 = zext i8 %1 to i32
8 store i32 %2, i32 addrspace(1)* %out
9 ret void
10 }
11
12 ; Load a f32 value from the constant address space.
13 ; CHECK: VTX_READ_32 T{{[0-9]+\.X, T[0-9]+\.X}}
14
15 define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) {
16 %1 = load float addrspace(2)* %in
17 store float %1, float addrspace(1)* %out
18 ret void
19 }
0 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: TEX
3 ;CHECK: ALU_PUSH
4 ;CHECK: JUMP @4
5 ;CHECK: ELSE @16
6 ;CHECK: TEX
7 ;CHECK: LOOP_START_DX10 @15
8 ;CHECK: LOOP_BREAK @14
9 ;CHECK: POP @16
10
11 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64"
12 target triple = "r600--"
13
14 define void @loop_ge(i32 addrspace(1)* nocapture %out, i32 %iterations) #0 {
15 entry:
16 %cmp5 = icmp sgt i32 %iterations, 0
17 br i1 %cmp5, label %for.body, label %for.end
18
19 for.body: ; preds = %for.body, %entry
20 %i.07.in = phi i32 [ %i.07, %for.body ], [ %iterations, %entry ]
21 %ai.06 = phi i32 [ %add, %for.body ], [ 0, %entry ]
22 %i.07 = add nsw i32 %i.07.in, -1
23 %arrayidx = getelementptr inbounds i32 addrspace(1)* %out, i32 %ai.06
24 store i32 %i.07, i32 addrspace(1)* %arrayidx, align 4, !tbaa !4
25 %add = add nsw i32 %ai.06, 1
26 %exitcond = icmp eq i32 %add, %iterations
27 br i1 %exitcond, label %for.end, label %for.body
28
29 for.end: ; preds = %for.body, %entry
30 ret void
31 }
32
33 attributes #0 = { nounwind "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" }
34
35 !opencl.kernels = !{!0, !1, !2, !3}
36
37 !0 = metadata !{void (i32 addrspace(1)*, i32)* @loop_ge}
38 !1 = metadata !{null}
39 !2 = metadata !{null}
40 !3 = metadata !{null}
41 !4 = metadata !{metadata !"int", metadata !5}
42 !5 = metadata !{metadata !"omnipotent char", metadata !6}
43 !6 = metadata !{metadata !"Simple C/C++ TBAA"}
+0
-44
test/CodeGen/R600/loop-adress.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: TEX
3 ;CHECK: ALU_PUSH
4 ;CHECK: JUMP @4
5 ;CHECK: ELSE @16
6 ;CHECK: TEX
7 ;CHECK: LOOP_START_DX10 @15
8 ;CHECK: LOOP_BREAK @14
9 ;CHECK: POP @16
10
11 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64"
12 target triple = "r600--"
13
14 define void @loop_ge(i32 addrspace(1)* nocapture %out, i32 %iterations) #0 {
15 entry:
16 %cmp5 = icmp sgt i32 %iterations, 0
17 br i1 %cmp5, label %for.body, label %for.end
18
19 for.body: ; preds = %for.body, %entry
20 %i.07.in = phi i32 [ %i.07, %for.body ], [ %iterations, %entry ]
21 %ai.06 = phi i32 [ %add, %for.body ], [ 0, %entry ]
22 %i.07 = add nsw i32 %i.07.in, -1
23 %arrayidx = getelementptr inbounds i32 addrspace(1)* %out, i32 %ai.06
24 store i32 %i.07, i32 addrspace(1)* %arrayidx, align 4, !tbaa !4
25 %add = add nsw i32 %ai.06, 1
26 %exitcond = icmp eq i32 %add, %iterations
27 br i1 %exitcond, label %for.end, label %for.body
28
29 for.end: ; preds = %for.body, %entry
30 ret void
31 }
32
33 attributes #0 = { nounwind "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" }
34
35 !opencl.kernels = !{!0, !1, !2, !3}
36
37 !0 = metadata !{void (i32 addrspace(1)*, i32)* @loop_ge}
38 !1 = metadata !{null}
39 !2 = metadata !{null}
40 !3 = metadata !{null}
41 !4 = metadata !{metadata !"int", metadata !5}
42 !5 = metadata !{metadata !"omnipotent char", metadata !6}
43 !6 = metadata !{metadata !"Simple C/C++ TBAA"}
0 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK-NOT: SETE
3 ;CHECK: CNDE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], 1.0, literal.x, [-0-9]+\(2.0}}
4 define void @test(float addrspace(1)* %out, float addrspace(1)* %in) {
5 %1 = load float addrspace(1)* %in
6 %2 = fcmp oeq float %1, 0.0
7 %3 = select i1 %2, float 1.0, float 2.0
8 store float %3, float addrspace(1)* %out
9 ret void
10 }
0 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK-NOT: SETE_INT
3 ;CHECK: CNDE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], 1, literal.x, 2}}
4 define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
5 %1 = load i32 addrspace(1)* %in
6 %2 = icmp eq i32 %1, 0
7 %3 = select i1 %2, i32 1, i32 2
8 store i32 %3, i32 addrspace(1)* %out
9 ret void
10 }
+0
-11
test/CodeGen/R600/selectcc_cnde.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK-NOT: SETE
3 ;CHECK: CNDE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], 1.0, literal.x, [-0-9]+\(2.0}}
4 define void @test(float addrspace(1)* %out, float addrspace(1)* %in) {
5 %1 = load float addrspace(1)* %in
6 %2 = fcmp oeq float %1, 0.0
7 %3 = select i1 %2, float 1.0, float 2.0
8 store float %3, float addrspace(1)* %out
9 ret void
10 }
+0
-11
test/CodeGen/R600/selectcc_cnde_int.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK-NOT: SETE_INT
3 ;CHECK: CNDE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], 1, literal.x, 2}}
4 define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
5 %1 = load i32 addrspace(1)* %in
6 %2 = icmp eq i32 %1, 0
7 %3 = select i1 %2, i32 1, i32 2
8 store i32 %3, i32 addrspace(1)* %out
9 ret void
10 }
0 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1 ;CHECK: SETE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
2
3 define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
4 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
5 %a = load <4 x i32> addrspace(1) * %in
6 %b = load <4 x i32> addrspace(1) * %b_ptr
7 %result = icmp eq <4 x i32> %a, %b
8 %sext = sext <4 x i1> %result to <4 x i32>
9 store <4 x i32> %sext, <4 x i32> addrspace(1)* %out
10 ret void
11 }
+0
-12
test/CodeGen/R600/setcc.v4i32.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1 ;CHECK: SETE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
2
3 define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
4 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
5 %a = load <4 x i32> addrspace(1) * %in
6 %b = load <4 x i32> addrspace(1) * %b_ptr
7 %result = icmp eq <4 x i32> %a, %b
8 %sext = sext <4 x i1> %result to <4 x i32>
9 store <4 x i32> %sext, <4 x i32> addrspace(1)* %out
10 ret void
11 }
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ; CHECK: @sint_to_fp_v4i32
3 ; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6 ; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
7
8 define void @sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
9 %value = load <4 x i32> addrspace(1) * %in
10 %result = sitofp <4 x i32> %value to <4 x float>
11 store <4 x float> %result, <4 x float> addrspace(1)* %out
12 ret void
13 }
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
11 ; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
22
3 ; CHECK: @store_float
3 ; floating-point store
4 ; EG-CHECK: @store_f32
45 ; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1
6 ; SI-CHECK: @store_f32
57 ; SI-CHECK: BUFFER_STORE_DWORD
68
7 define void @store_float(float addrspace(1)* %out, float %in) {
9 define void @store_f32(float addrspace(1)* %out, float %in) {
810 store float %in, float addrspace(1)* %out
911 ret void
1012 }
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
1
2 ; XXX: Merge this test into store.ll once it is supported on SI
3
4 ; v4i32 store
5 ; EG-CHECK: @store_v4i32
6 ; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
7
8 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
9 %1 = load <4 x i32> addrspace(1) * %in
10 store <4 x i32> %1, <4 x i32> addrspace(1)* %out
11 ret void
12 }
13
14 ; v4f32 store
15 ; EG-CHECK: @store_v4f32
16 ; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
17 define void @store_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
18 %1 = load <4 x float> addrspace(1) * %in
19 store <4 x float> %1, <4 x float> addrspace(1)* %out
20 ret void
21 }
+0
-9
test/CodeGen/R600/store.v4f32.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
3
4 define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
5 %1 = load <4 x float> addrspace(1) * %in
6 store <4 x float> %1, <4 x float> addrspace(1)* %out
7 ret void
8 }
+0
-9
test/CodeGen/R600/store.v4i32.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
3
4 define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
5 %1 = load <4 x i32> addrspace(1) * %in
6 store <4 x i32> %1, <4 x i32> addrspace(1)* %out
7 ret void
8 }
0 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;The code generated by udiv is long and complex and may frequently change.
3 ;The goal of this test is to make sure the ISel doesn't fail when it gets
4 ;a v4i32 udiv
5 ;CHECK: RETURN
6
7 define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
8 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
9 %a = load <4 x i32> addrspace(1) * %in
10 %b = load <4 x i32> addrspace(1) * %b_ptr
11 %result = udiv <4 x i32> %a, %b
12 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
13 ret void
14 }
+0
-15
test/CodeGen/R600/udiv.v4i32.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;The code generated by udiv is long and complex and may frequently change.
3 ;The goal of this test is to make sure the ISel doesn't fail when it gets
4 ;a v4i32 udiv
5 ;CHECK: RETURN
6
7 define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
8 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
9 %a = load <4 x i32> addrspace(1) * %in
10 %b = load <4 x i32> addrspace(1) * %b_ptr
11 %result = udiv <4 x i32> %a, %b
12 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
13 ret void
14 }
0 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ; CHECK: @uint_to_fp_v4i32
3 ; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6 ; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
7
8 define void @uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
9 %value = load <4 x i32> addrspace(1) * %in
10 %result = uitofp <4 x i32> %value to <4 x float>
11 store <4 x float> %result, <4 x float> addrspace(1)* %out
12 ret void
13 }
0 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;The code generated by urem is long and complex and may frequently change.
3 ;The goal of this test is to make sure the ISel doesn't fail when it gets
4 ;a v4i32 urem
5 ;CHECK: RETURN
6
7 define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
8 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
9 %a = load <4 x i32> addrspace(1) * %in
10 %b = load <4 x i32> addrspace(1) * %b_ptr
11 %result = urem <4 x i32> %a, %b
12 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
13 ret void
14 }
+0
-15
test/CodeGen/R600/urem.v4i32.ll less more
None ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ;The code generated by urem is long and complex and may frequently change.
3 ;The goal of this test is to make sure the ISel doesn't fail when it gets
4 ;a v4i32 urem
5 ;CHECK: RETURN
6
7 define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
8 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
9 %a = load <4 x i32> addrspace(1) * %in
10 %b = load <4 x i32> addrspace(1) * %b_ptr
11 %result = urem <4 x i32> %a, %b
12 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
13 ret void
14 }
+0
-53
test/CodeGen/R600/vec4-expand.ll less more
None ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
1
2 ; CHECK: @fp_to_sint
3 ; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
4 ; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5 ; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6 ; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
7
8 define void @fp_to_sint(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
9 %value = load <4 x float> addrspace(1) * %in
10 %result = fptosi <4 x float> %value to <4 x i32>
11 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
12 ret void
13 }
14
15 ; CHECK: @fp_to_uint
16 ; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
17 ; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
18 ; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
19 ; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
20
21 define void @fp_to_uint(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
22 %value = load <4 x float> addrspace(1) * %in
23 %result = fptoui <4 x float> %value to <4 x i32>
24 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
25 ret void
26 }
27
28 ; CHECK: @sint_to_fp
29 ; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
30 ; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
31 ; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
32 ; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
33
34 define void @sint_to_fp(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
35 %value = load <4 x i32> addrspace(1) * %in
36 %result = sitofp <4 x i32> %value to <4 x float>
37 store <4 x float> %result, <4 x float> addrspace(1)* %out
38 ret void
39 }
40
41 ; CHECK: @uint_to_fp
42 ; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
43 ; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
44 ; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
45 ; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
46
47 define void @uint_to_fp(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
48 %value = load <4 x i32> addrspace(1) * %in
49 %result = uitofp <4 x i32> %value to <4 x float>
50 store <4 x float> %result, <4 x float> addrspace(1)* %out
51 ret void
52 }