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[AMDGPU][MC] Enabled parsing of relocations on VALU instructions See bug 37566: https://bugs.llvm.org/show_bug.cgi?id=37566 Reviewers: artem.tamazov, arsenm, nhaehnle Differential Revision: https://reviews.llvm.org/D47884 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334622 91177308-0d34-0410-b5e6-96231b3b80d8 Dmitry Preobrazhensky 2 years ago
3 changed file(s) with 20 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
442442 }
443443
444444 bool isVSrcB32() const {
445 return isVCSrcF32() || isLiteralImm(MVT::i32);
445 return isVCSrcF32() || isLiteralImm(MVT::i32) || isExpr();
446446 }
447447
448448 bool isVSrcB64() const {
459459 }
460460
461461 bool isVSrcF32() const {
462 return isVCSrcF32() || isLiteralImm(MVT::f32);
462 return isVCSrcF32() || isLiteralImm(MVT::f32) || isExpr();
463463 }
464464
465465 bool isVSrcF64() const {
3939 s_mov_b32 s0, foo+2
4040 // VI: s_mov_b32 s0, 514 ; encoding: [0xff,0x00,0x80,0xbe,0x02,0x02,0x00,0x00]
4141
42 v_mul_f32 v0, foo+2, v2
43 // VI: v_mul_f32_e32 v0, 514, v2 ; encoding: [0xff,0x04,0x00,0x0a,0x02,0x02,0x00,0x00]
44
4245 BB1:
4346 v_nop_e64
4447 BB2:
11
22 // CHECK: Relocations [
33 // CHECK: .rel.text {
4 // CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
5 // CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
6 // CHECK: R_AMDGPU_GOTPCREL global_var0 0x0
7 // CHECK: R_AMDGPU_GOTPCREL32_LO global_var1 0x0
8 // CHECK: R_AMDGPU_GOTPCREL32_HI global_var2 0x0
9 // CHECK: R_AMDGPU_REL32_LO global_var3 0x0
10 // CHECK: R_AMDGPU_REL32_HI global_var4 0x0
411 // CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
512 // CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
613 // CHECK: R_AMDGPU_GOTPCREL global_var0 0x0
2532 s_mov_b32 s5, global_var3@rel32@lo
2633 s_mov_b32 s6, global_var4@rel32@hi
2734
35 v_mov_b32 v0, SCRATCH_RSRC_DWORD0
36 v_mov_b32 v1, SCRATCH_RSRC_DWORD1
37 v_mov_b32 v2, global_var0@GOTPCREL
38 v_mov_b32 v3, global_var1@gotpcrel32@lo
39 v_mov_b32 v4, global_var2@gotpcrel32@hi
40 v_mov_b32 v5, global_var3@rel32@lo
41 v_mov_b32 v6, global_var4@rel32@hi
42
2843 .globl global_var0
2944 .globl global_var1
3045 .globl global_var2