llvm.org GIT mirror llvm / 3a89b36
[x86] change names of vector splitting helper functions; NFC As the code comments suggest, these are about splitting, and they are not necessarily limited to lowering, so that misled me. There's nothing that's actually x86-specific in these either, so they might be better placed in a common header so any target can use them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342575 91177308-0d34-0410-b5e6-96231b3b80d8 Sanjay Patel 1 year, 9 months ago
1 changed file(s) with 15 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
2283122831
2283222832 /// Break a 256-bit integer operation into two new 128-bit ones and then
2283322833 /// concatenate the result back.
22834 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
22834 static SDValue split256IntArith(SDValue Op, SelectionDAG &DAG) {
2283522835 MVT VT = Op.getSimpleValueType();
2283622836
2283722837 assert(VT.is256BitVector() && VT.isInteger() &&
2286022860
2286122861 /// Break a 512-bit integer operation into two new 256-bit ones and then
2286222862 /// concatenate the result back.
22863 static SDValue Lower512IntArith(SDValue Op, SelectionDAG &DAG) {
22863 static SDValue split512IntArith(SDValue Op, SelectionDAG &DAG) {
2286422864 MVT VT = Op.getSimpleValueType();
2286522865
2286622866 assert(VT.is512BitVector() && VT.isInteger() &&
2289522895 assert(Op.getSimpleValueType().is256BitVector() &&
2289622896 Op.getSimpleValueType().isInteger() &&
2289722897 "Only handle AVX 256-bit vector integer operation");
22898 return Lower256IntArith(Op, DAG);
22898 return split256IntArith(Op, DAG);
2289922899 }
2290022900
2290122901 static SDValue LowerABS(SDValue Op, SelectionDAG &DAG) {
2292322923
2292422924 // For AVX1 cases, split to use legal ops (everything but v4i64).
2292522925 if (VT.getScalarType() != MVT::i64 && VT.is256BitVector())
22926 return Lower256IntArith(Op, DAG);
22926 return split256IntArith(Op, DAG);
2292722927
2292822928 SDLoc DL(Op);
2292922929 unsigned Opcode = Op.getOpcode();
2296522965 if (VT.getScalarType() == MVT::i1)
2296622966 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
2296722967
22968 // Decompose 256-bit ops into smaller 128-bit ops.
22968 // Decompose 256-bit ops into 128-bit ops.
2296922969 if (VT.is256BitVector() && !Subtarget.hasInt256())
22970 return Lower256IntArith(Op, DAG);
22970 return split256IntArith(Op, DAG);
2297122971
2297222972 SDValue A = Op.getOperand(0);
2297322973 SDValue B = Op.getOperand(1);
2297922979 // For 512-bit vectors, split into 256-bit vectors to allow the
2298022980 // sign-extension to occur.
2298122981 if (VT == MVT::v64i8)
22982 return Lower512IntArith(Op, DAG);
22982 return split512IntArith(Op, DAG);
2298322983
2298422984 // For 256-bit vectors, split into 128-bit vectors to allow the
2298522985 // sign-extension to occur. We don't need this on AVX512BW as we can
2298622986 // safely sign-extend to v32i16.
2298722987 if (VT == MVT::v32i8 && !Subtarget.hasBWI())
22988 return Lower256IntArith(Op, DAG);
22988 return split256IntArith(Op, DAG);
2298922989
2299022990 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
2299122991 return DAG.getNode(
2311623116 SDValue A = Op.getOperand(0);
2311723117 SDValue B = Op.getOperand(1);
2311823118
23119 // Decompose 256-bit ops into smaller 128-bit ops.
23119 // Decompose 256-bit ops into 128-bit ops.
2312023120 if (VT.is256BitVector() && !Subtarget.hasInt256())
23121 return Lower256IntArith(Op, DAG);
23121 return split256IntArith(Op, DAG);
2312223122
2312323123 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32) {
2312423124 assert((VT == MVT::v4i32 && Subtarget.hasSSE2()) ||
2320123201 // For 512-bit vectors, split into 256-bit vectors to allow the
2320223202 // sign-extension to occur.
2320323203 if (VT == MVT::v64i8)
23204 return Lower512IntArith(Op, DAG);
23204 return split512IntArith(Op, DAG);
2320523205
2320623206 // AVX2 implementations - extend xmm subvectors to ymm.
2320723207 if (Subtarget.hasInt256()) {
2425624256 return R;
2425724257 }
2425824258
24259 // Decompose 256-bit shifts into smaller 128-bit shifts.
24259 // Decompose 256-bit shifts into 128-bit shifts.
2426024260 if (VT.is256BitVector())
24261 return Lower256IntArith(Op, DAG);
24261 return split256IntArith(Op, DAG);
2426224262
2426324263 return SDValue();
2426424264 }
2429824298 // XOP has 128-bit vector variable + immediate rotates.
2429924299 // +ve/-ve Amt = rotate left/right - just need to handle ISD::ROTL.
2430024300 if (Subtarget.hasXOP()) {
24301 // Split 256-bit integers.
2430224301 if (VT.is256BitVector())
24303 return Lower256IntArith(Op, DAG);
24302 return split256IntArith(Op, DAG);
2430424303 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
2430524304
2430624305 // Attempt to rotate by immediate.
2431924318
2432024319 // Split 256-bit integers on pre-AVX2 targets.
2432124320 if (VT.is256BitVector() && !Subtarget.hasAVX2())
24322 return Lower256IntArith(Op, DAG);
24321 return split256IntArith(Op, DAG);
2432324322
2432424323 assert((VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8 ||
2432524324 ((VT == MVT::v8i32 || VT == MVT::v16i16 || VT == MVT::v32i8) &&