llvm.org GIT mirror llvm / 3a5cc55
[X86] LowerAVXExtend - handle ANY_EXTEND_VECTOR_INREG lowering as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363922 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim a month ago
1 changed file(s) with 10 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
1852018520
1852118521 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
1852218522 const X86Subtarget &Subtarget) {
18523 MVT VT = Op->getSimpleValueType(0);
18524 SDValue In = Op->getOperand(0);
18523 MVT VT = Op.getSimpleValueType();
18524 SDValue In = Op.getOperand(0);
1852518525 MVT InVT = In.getSimpleValueType();
1852618526 SDLoc dl(Op);
18527 unsigned Opc = Op.getOpcode();
1852718528
1852818529 assert(VT.isVector() && InVT.isVector() && "Expected vector type");
18530 assert((Opc == ISD::ANY_EXTEND || Opc == ISD::ZERO_EXTEND) &&
18531 "Unexpected extension opcode");
1852918532 assert(VT.getVectorNumElements() == VT.getVectorNumElements() &&
1853018533 "Expected same number of elements");
1853118534 assert((VT.getVectorElementType() == MVT::i16 ||
1853718540 InVT.getVectorElementType() == MVT::i32) &&
1853818541 "Unexpected element type");
1853918542
18543 unsigned ExtendInVecOpc = getOpcode_EXTEND_VECTOR_INREG(Opc);
18544
1854018545 // Custom legalize v8i8->v8i64 on CPUs without avx512bw.
1854118546 if (InVT == MVT::v8i8) {
1854218547 if (!ExperimentalVectorWideningLegalization || VT != MVT::v8i64)
1854418549
1854518550 In = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op),
1854618551 MVT::v16i8, In, DAG.getUNDEF(MVT::v8i8));
18547 // FIXME: This should be ANY_EXTEND_VECTOR_INREG for ANY_EXTEND input.
18548 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, dl, VT, In);
18552 return DAG.getNode(ExtendInVecOpc, dl, VT, In);
1854918553 }
1855018554
1855118555 if (Subtarget.hasInt256())
1856718571 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
1856818572 VT.getVectorNumElements() / 2);
1856918573
18570 SDValue OpLo = DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, dl, HalfVT, In);
18574 SDValue OpLo = DAG.getNode(ExtendInVecOpc, dl, HalfVT, In);
1857118575
1857218576 // Short-circuit if we can determine that each 128-bit half is the same value.
1857318577 // Otherwise, this is difficult to match and optimize.
1857718581
1857818582 SDValue ZeroVec = DAG.getConstant(0, dl, InVT);
1857918583 SDValue Undef = DAG.getUNDEF(InVT);
18580 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
18584 bool NeedZero = Opc == ISD::ZERO_EXTEND;
1858118585 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
1858218586 OpHi = DAG.getBitcast(HalfVT, OpHi);
1858318587