llvm.org GIT mirror llvm / 39e7554
Materialize 64-bit immediates. The last resort pattern produces 6 instructions, and there are still opportunities for materializing some immediates in fewer instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178526 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 7 years ago
2 changed file(s) with 134 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
4444 defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
4545
4646 } // Predicates = [Is64Bit]
47
48
49 //===----------------------------------------------------------------------===//
50 // 64-bit Immediates.
51 //===----------------------------------------------------------------------===//
52 //
53 // All 32-bit immediates can be materialized with sethi+or, but 64-bit
54 // immediates may require more code. There may be a point where it is
55 // preferable to use a constant pool load instead, depending on the
56 // microarchitecture.
57
58 // The %g0 register is constant 0.
59 // This is useful for stx %g0, [...], for example.
60 def : Pat<(i64 0), (i64 G0)>, Requires<[Is64Bit]>;
61
62 // Single-instruction patterns.
63
64 // The ALU instructions want their simm13 operands as i32 immediates.
65 def as_i32imm : SDNodeXForm
66 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
67 }]>;
68 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
69 def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
70
71 // Double-instruction patterns.
72
73 // All unsigned i32 immediates can be handled by sethi+or.
74 def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
75 def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,
76 Requires<[Is64Bit]>;
77
78 // All negative i33 immediates can be handled by sethi+xor.
79 def nimm33 : PatLeaf<(imm), [{
80 int64_t Imm = N->getSExtValue();
81 return Imm < 0 && isInt<33>(Imm);
82 }]>;
83 // Bits 10-31 inverted. Same as assembler's %hix.
84 def HIX22 : SDNodeXForm
85 uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1);
86 return CurDAG->getTargetConstant(Val, MVT::i32);
87 }]>;
88 // Bits 0-9 with ones in bits 10-31. Same as assembler's %lox.
89 def LOX10 : SDNodeXForm
90 return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), MVT::i32);
91 }]>;
92 def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
93 Requires<[Is64Bit]>;
94
95 // More possible patterns:
96 //
97 // (sllx sethi, n)
98 // (sllx simm13, n)
99 //
100 // 3 instrs:
101 //
102 // (xor (sllx sethi), simm13)
103 // (sllx (xor sethi, simm13))
104 //
105 // 4 instrs:
106 //
107 // (or sethi, (sllx sethi))
108 // (xnor sethi, (sllx sethi))
109 //
110 // 5 instrs:
111 //
112 // (or (sllx sethi), (or sethi, simm13))
113 // (xnor (sllx sethi), (or sethi, simm13))
114 // (or (sllx sethi), (sllx sethi))
115 // (xnor (sllx sethi), (sllx sethi))
116 //
117 // Worst case is 6 instrs:
118 //
119 // (or (sllx (or sethi, simmm13)), (or sethi, simm13))
120
121 // Bits 42-63, same as assembler's %hh.
122 def HH22 : SDNodeXForm
123 uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1);
124 return CurDAG->getTargetConstant(Val, MVT::i32);
125 }]>;
126 // Bits 32-41, same as assembler's %hm.
127 def HM10 : SDNodeXForm
128 uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1);
129 return CurDAG->getTargetConstant(Val, MVT::i32);
130 }]>;
131 def : Pat<(i64 imm:$val),
132 (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i64 32)),
133 (ORri (SETHIi (HI22 $val)), (LO10 $val)))>,
134 Requires<[Is64Bit]>;
1818 %x = ashr i64 %a, %b
1919 ret i64 %x
2020 }
21
22 ; Immediate materialization. Many of these patterns could actually be merged
23 ; into the restore instruction:
24 ;
25 ; restore %g0, %g0, %o0
26 ;
27 ; CHECK: ret_imm0
28 ; CHECK: or %g0, %g0, %i0
29 define i64 @ret_imm0() {
30 ret i64 0
31 }
32
33 ; CHECK: ret_simm13
34 ; CHECK: or %g0, -4096, %i0
35 define i64 @ret_simm13() {
36 ret i64 -4096
37 }
38
39 ; CHECK: ret_sethi
40 ; CHECK: sethi 4, %i0
41 ; CHECK-NOT: or
42 ; CHECK: restore
43 define i64 @ret_sethi() {
44 ret i64 4096
45 }
46
47 ; CHECK: ret_sethi
48 ; CHECK: sethi 4, [[R:%[goli][0-7]]]
49 ; CHECK: or [[R]], 1, %i0
50 define i64 @ret_sethi_or() {
51 ret i64 4097
52 }
53
54 ; CHECK: ret_nimm33
55 ; CHECK: sethi 4, [[R:%[goli][0-7]]]
56 ; CHECK: xor [[R]], -4, %i0
57 define i64 @ret_nimm33() {
58 ret i64 -4100
59 }
60
61 ; CHECK: ret_bigimm
62 ; CHECK: sethi
63 ; CHECK: sethi
64 define i64 @ret_bigimm() {
65 ret i64 6800754272627607872
66 }