llvm.org GIT mirror llvm / 39dfb0f
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 8 years ago
24 changed file(s) with 165 addition(s) and 154 deletion(s). Raw diff Collapse all Expand all
2020 // ARM Subtarget features.
2121 //
2222
23 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
23 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
2424 "Enable VFP2 instructions">;
25 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
26 "Enable VFP3 instructions">;
27 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
28 "Enable NEON instructions">;
25 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
26 "Enable VFP3 instructions",
27 [FeatureVFP2]>;
28 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
29 "Enable NEON instructions",
30 [FeatureVFP3]>;
2931 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
3032 "Enable Thumb2 instructions">;
3133 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
8385 "Supports Multiprocessing extension">;
8486
8587 // ARM architectures.
86 def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
88 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
8789 "ARM v4T">;
88 def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
89 "ARM v5T">;
90 def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
91 "ARM v5TE, v5TEj, v5TExp">;
92 def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
93 "ARM v6">;
94 def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
95 "ARM v6m",
96 [FeatureNoARM, FeatureDB]>;
97 def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
90 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
91 "ARM v5T",
92 [HasV4TOps]>;
93 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
94 "ARM v5TE, v5TEj, v5TExp",
95 [HasV5TOps]>;
96 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
97 "ARM v6",
98 [HasV5TEOps]>;
99 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
98100 "ARM v6t2",
99 [FeatureThumb2, FeatureDSPThumb2]>;
100 def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
101 "ARM v7A",
102 [FeatureThumb2, FeatureNEON, FeatureDB,
103 FeatureDSPThumb2]>;
104 def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
105 "ARM v7M",
106 [FeatureThumb2, FeatureNoARM, FeatureDB,
107 FeatureHWDiv]>;
108 def ArchV7EM : SubtargetFeature<"v7em", "ARMArchVersion", "V7EM",
109 "ARM v7E-M",
110 [FeatureThumb2, FeatureNoARM, FeatureDB,
111 FeatureHWDiv, FeatureDSPThumb2,
112 FeatureT2XtPk]>;
101 [HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>;
102 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
103 "ARM v7",
104 [HasV6T2Ops]>;
113105
114106 //===----------------------------------------------------------------------===//
115107 // ARM Processors supported.
144136 def : ProcNoItin<"strongarm1110", []>;
145137
146138 // V4T Processors.
147 def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
148 def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
149 def : ProcNoItin<"arm710t", [ArchV4T]>;
150 def : ProcNoItin<"arm720t", [ArchV4T]>;
151 def : ProcNoItin<"arm9", [ArchV4T]>;
152 def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
153 def : ProcNoItin<"arm920", [ArchV4T]>;
154 def : ProcNoItin<"arm920t", [ArchV4T]>;
155 def : ProcNoItin<"arm922t", [ArchV4T]>;
156 def : ProcNoItin<"arm940t", [ArchV4T]>;
157 def : ProcNoItin<"ep9312", [ArchV4T]>;
139 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
140 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
141 def : ProcNoItin<"arm710t", [HasV4TOps]>;
142 def : ProcNoItin<"arm720t", [HasV4TOps]>;
143 def : ProcNoItin<"arm9", [HasV4TOps]>;
144 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
145 def : ProcNoItin<"arm920", [HasV4TOps]>;
146 def : ProcNoItin<"arm920t", [HasV4TOps]>;
147 def : ProcNoItin<"arm922t", [HasV4TOps]>;
148 def : ProcNoItin<"arm940t", [HasV4TOps]>;
149 def : ProcNoItin<"ep9312", [HasV4TOps]>;
158150
159151 // V5T Processors.
160 def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
161 def : ProcNoItin<"arm1020t", [ArchV5T]>;
152 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
153 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
162154
163155 // V5TE Processors.
164 def : ProcNoItin<"arm9e", [ArchV5TE]>;
165 def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
166 def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
167 def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
168 def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
169 def : ProcNoItin<"arm10e", [ArchV5TE]>;
170 def : ProcNoItin<"arm1020e", [ArchV5TE]>;
171 def : ProcNoItin<"arm1022e", [ArchV5TE]>;
172 def : ProcNoItin<"xscale", [ArchV5TE]>;
173 def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
156 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
157 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
158 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
159 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
160 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
161 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
162 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
163 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
164 def : ProcNoItin<"xscale", [HasV5TEOps]>;
165 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
174166
175167 // V6 Processors.
176 def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>;
177 def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
178 FeatureHasSlowFPVMLx]>;
179 def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>;
180 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
181 FeatureHasSlowFPVMLx]>;
182 def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>;
183 def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2,
168 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
169 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
170 FeatureHasSlowFPVMLx]>;
171 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
172 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
173 FeatureHasSlowFPVMLx]>;
174 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
175 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
184176 FeatureHasSlowFPVMLx]>;
185177
186178 // V6M Processors.
187 def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>;
179 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
180 FeatureDB]>;
188181
189182 // V6T2 Processors.
190 def : Processor<"arm1156t2-s", ARMV6Itineraries, [ArchV6T2]>;
191 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ArchV6T2, FeatureVFP2,
192 FeatureHasSlowFPVMLx]>;
193
194 // V7 Processors.
183 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops]>;
184 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
185 FeatureHasSlowFPVMLx]>;
186
187 // V7a Processors.
195188 def : Processor<"cortex-a8", CortexA8Itineraries,
196 [ArchV7A, ProcA8]>;
189 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
190 FeatureDSPThumb2]>;
197191 def : Processor<"cortex-a9", CortexA9Itineraries,
198 [ArchV7A, ProcA9]>;
192 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
193 FeatureDSPThumb2]>;
199194 def : Processor<"cortex-a9-mp", CortexA9Itineraries,
200 [ArchV7A, ProcA9, FeatureMP]>;
195 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
196 FeatureDSPThumb2, FeatureMP]>;
201197
202198 // V7M Processors.
203 def : ProcNoItin<"cortex-m3", [ArchV7M]>;
204 def : ProcNoItin<"cortex-m4", [ArchV7EM, FeatureVFP2, FeatureVFPOnlySP]>;
199 def : ProcNoItin<"cortex-m3", [HasV7Ops,
200 FeatureThumb2, FeatureNoARM, FeatureDB,
201 FeatureHWDiv]>;
202
203 // V7EM Processors.
204 def : ProcNoItin<"cortex-m4", [HasV7Ops,
205 FeatureThumb2, FeatureNoARM, FeatureDB,
206 FeatureHWDiv, FeatureDSPThumb2,
207 FeatureT2XtPk, FeatureVFP2,
208 FeatureVFPOnlySP]>;
205209
206210 //===----------------------------------------------------------------------===//
207211 // Register File Description
3838 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
3939 const std::string &FS)
4040 : ARMGenSubtargetInfo()
41 , ARMArchVersion(V4)
4241 , ARMProcFamily(Others)
43 , ARMFPUType(None)
42 , HasV4TOps(false)
43 , HasV5TOps(false)
44 , HasV5TEOps(false)
45 , HasV6Ops(false)
46 , HasV6T2Ops(false)
47 , HasV7Ops(false)
48 , HasVFPv2(false)
49 , HasVFPv3(false)
50 , HasNEON(false)
4451 , UseNEONForSinglePrecisionFP(false)
4552 , SlowFPVMLx(false)
4653 , HasVMLxForwarding(false)
8895
8996 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
9097 // ARM version or CPU and then remove this.
91 if (ARMArchVersion < V6T2 && hasThumb2())
92 ARMArchVersion = V6T2;
98 if (!HasV6T2Ops && hasThumb2())
99 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
93100
94101 // Initialize scheduling itinerary for the specified CPU.
95102 InstrItins = getInstrItineraryForCPU(CPUString);
103110 if (!isTargetDarwin())
104111 UseMovt = hasV6T2Ops();
105112 else {
106 IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
113 IsR9Reserved = ReserveR9 | !HasV6Ops;
107114 UseMovt = DarwinUseMOVT && hasV6T2Ops();
108115 }
109116
2727
2828 class ARMSubtarget : public ARMGenSubtargetInfo {
2929 protected:
30 enum ARMArchEnum {
31 V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M, V7EM
32 };
33
3430 enum ARMProcFamilyEnum {
3531 Others, CortexA8, CortexA9
3632 };
3733
38 enum ARMFPEnum {
39 None, VFPv2, VFPv3, NEON
40 };
41
42 /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
43 /// V6, V6T2, V7A, V7M, V7EM.
44 ARMArchEnum ARMArchVersion;
45
4634 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
4735 ARMProcFamilyEnum ARMProcFamily;
4836
49 /// ARMFPUType - Floating Point Unit type.
50 ARMFPEnum ARMFPUType;
37 /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
38 /// Specify whether target support specific ARM ISA variants.
39 bool HasV4TOps;
40 bool HasV5TOps;
41 bool HasV5TEOps;
42 bool HasV6Ops;
43 bool HasV6T2Ops;
44 bool HasV7Ops;
45
46 /// HasVFPv2, HasVFPv3, HasNEON - Specify what floating point ISAs are
47 /// supported.
48 bool HasVFPv2;
49 bool HasVFPv3;
50 bool HasNEON;
5151
5252 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
5353 /// specified. Use the method useNEONForSinglePrecisionFP() to
171171
172172 void computeIssueWidth();
173173
174 bool hasV4TOps() const { return ARMArchVersion >= V4T; }
175 bool hasV5TOps() const { return ARMArchVersion >= V5T; }
176 bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
177 bool hasV6Ops() const { return ARMArchVersion >= V6; }
178 bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
179 bool hasV7Ops() const { return ARMArchVersion >= V7A; }
174 bool hasV4TOps() const { return HasV4TOps; }
175 bool hasV5TOps() const { return HasV5TOps; }
176 bool hasV5TEOps() const { return HasV5TEOps; }
177 bool hasV6Ops() const { return HasV6Ops; }
178 bool hasV6T2Ops() const { return HasV6T2Ops; }
179 bool hasV7Ops() const { return HasV7Ops; }
180180
181181 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
182182 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
183183
184184 bool hasARMOps() const { return !NoARM; }
185185
186 bool hasVFP2() const { return ARMFPUType >= VFPv2; }
187 bool hasVFP3() const { return ARMFPUType >= VFPv3; }
188 bool hasNEON() const { return ARMFPUType >= NEON; }
186 bool hasVFP2() const { return HasVFPv2; }
187 bool hasVFP3() const { return HasVFPv3; }
188 bool hasNEON() const { return HasNEON; }
189189 bool useNEONForSinglePrecisionFP() const {
190190 return hasNEON() && UseNEONForSinglePrecisionFP; }
191
191192 bool hasDivide() const { return HasHardwareDivide; }
192193 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
193194 bool hasDataBarrier() const { return HasDataBarrier; }
9090 if (Idx) {
9191 unsigned SubVer = TT[Idx];
9292 if (SubVer >= '7' && SubVer <= '9') {
93 ARMArchFeature = "+v7a";
9493 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
95 ARMArchFeature = "+v7m";
94 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv
95 ARMArchFeature = "+v7,+noarm,+db,+hwdiv";
9696 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
97 ARMArchFeature = "+v7em";
98 }
97 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
98 // FeatureT2XtPk
99 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk";
100 } else
101 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2
102 ARMArchFeature = "+v7,+neon,+db,+t2dsp";
99103 } else if (SubVer == '6') {
100 ARMArchFeature = "+v6";
101 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') {
104 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
102105 ARMArchFeature = "+v6t2";
103 }
106 else
107 ARMArchFeature = "+v6";
104108 } else if (SubVer == '5') {
105 ARMArchFeature = "+v5t";
106 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') {
109 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
107110 ARMArchFeature = "+v5te";
108 }
109 } else if (SubVer == '4') {
110 if (Len >= Idx+2 && TT[Idx+1] == 't') {
111 ARMArchFeature = "+v4t";
112 } else {
113 ARMArchFeature = "";
114 }
115 }
111 else
112 ARMArchFeature = "+v5t";
113 } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
114 ARMArchFeature = "+v4t";
116115 }
117116
118117 return ARMArchFeature;
None ; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
0 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s
11 ; This test checks that the address of the varg arguments is correctly
22 ; computed when there are 5 or more regular arguments.
33
0 ; RUN: llc %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \
11 ; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=BASIC %s
22 ; RUN: llc %s -mtriple=armv7-linux-gnueabi -march=arm -mcpu=cortex-a8 \
3 ; RUN: -mattr=-neon -mattr=+vfp2 \
3 ; RUN: -mattr=-neon,-vfp3,+vfp2 \
44 ; RUN: -arm-reserve-r9 -filetype=obj -o - | \
55 ; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=CORTEXA8 %s
66
None ; RUN: llc < %s -mtriple=arm-unknown-eabi | FileCheck %s -check-prefix=THUMB
1 ; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM
2 ; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB
3 ; RUN: llc < %s -mtriple=arm-unknown-eabi -mattr=+v6 | FileCheck %s -check-prefix=THUMB
0 ; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB
1 ; RUN: llc < %s -mtriple=armv4-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM
2 ; RUN: llc < %s -mtriple=armv7-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB
3 ; RUN: llc < %s -mtriple=armv6-unknown-eabi | FileCheck %s -check-prefix=THUMB
44 ; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM
55 ; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB
66
None ; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s
0 ; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s
11
22 define i32 @sbfx1(i32 %a) {
33 ; CHECK: sbfx1
None ; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECKV4
0 ; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s -check-prefix=CHECKV4
11 ; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5
2 ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\
2 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi\
33 ; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF
44
55 @t = weak global i32 ()* null ; [#uses=1]
None ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic
1 ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic
2 ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC
3 ; RUN: llc < %s -mtriple=arm-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC
0 ; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic
1 ; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic
2 ; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC
3 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC
44
55 @G = external global i32
66
0 ; RUN: llc < %s -march=arm
1 ; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | count 1
2 ; RUN: llc < %s -mtriple=arm-linux-gnu --disable-fp-elim | \
1 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi | grep mov | count 1
2 ; RUN: llc < %s -mtriple=armv6-linux-gnu --disable-fp-elim | \
33 ; RUN: grep mov | count 2
4 ; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 2
4 ; RUN: llc < %s -mtriple=armv6-apple-darwin | grep mov | count 2
55
66 @str = internal constant [12 x i8] c"Hello World\00"
77
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
11
22 ;; Integer absolute value, should produce something as good as: ARM:
33 ;; add r3, r0, r0, asr #31
None ; RUN: llc < %s -march=arm
1 ; RUN: llc < %s -march=arm | grep bx | count 1
0 ; RUN: llc < %s -march=arm -mattr=+v4t
1 ; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 1
22
33 define i32 @t1(i32 %a, i32 %b) {
44 %tmp2 = icmp eq i32 %a, 0
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
11
22 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
33 ; CHECK: t1:
None ; RUN: llc < %s -march=arm
1 ; RUN: llc < %s -march=arm | grep cmpne | count 1
2 ; RUN: llc < %s -march=arm | grep bx | count 2
0 ; RUN: llc < %s -march=arm -mattr=+v4t
1 ; RUN: llc < %s -march=arm -mattr=+v4t | grep cmpne | count 1
2 ; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2
33
44 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
55 switch i32 %c, label %cond_next [
None ; RUN: llc < %s -relocation-model=pic -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=ARM
1 ; RUN: llc < %s -relocation-model=pic -mtriple=thumb-apple-darwin | FileCheck %s -check-prefix=THUMB
0 ; RUN: llc < %s -relocation-model=pic -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=ARM
1 ; RUN: llc < %s -relocation-model=pic -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=THUMB
22 ; RUN: llc < %s -relocation-model=static -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB2
33
44 @nextaddr = global i8* null ; [#uses=2]
None ; RUN: llc < %s -march=arm | not grep mov
0 ; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov
11
22 define i32 @f1() {
33 %buf = alloca [32 x i32], align 4
None ; RUN: llc -march=arm < %s | FileCheck %s
0 ; RUN: llc -march=arm -mattr=+v4t < %s | FileCheck %s
11 ;
22
33 define i32 @test1(i1 %a, i32* %b) {
1919 %r = load i32* %gep
2020 ; CHECK-NEXT: bx lr
2121 ret i32 %r
22 }
22 }
0 ; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld
1 ; RUN: llc < %s -march=thumb -mattr=+v7a | FileCheck %s -check-prefix=THUMB2
2 ; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s -check-prefix=ARM
1 ; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2
2 ; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s -check-prefix=ARM
33 ; RUN: llc < %s -march=arm -mcpu=cortex-a9-mp | FileCheck %s -check-prefix=ARM-MP
44 ; rdar://8601536
55
None ; RUN: llc < %s -march=arm | not grep orr
1 ; RUN: llc < %s -march=arm | not grep mov
0 ; RUN: llc < %s -march=arm -mattr=+v4t | not grep orr
1 ; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov
22
33 define void @bar(i8* %P, i16* %Q) {
44 entry:
0 ; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=V6
11 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=-db | FileCheck %s -check-prefix=V6
2 ; RUN: llc < %s -march=thumb -mattr=+v6m | FileCheck %s -check-prefix=V6M
2 ; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=V6M
33
44 declare void @llvm.memory.barrier(i1 , i1 , i1 , i1 , i1)
55
None ; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | FileCheck %s
0 ; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7 | FileCheck %s
11
22 define i32 @f1(i32 %a) {
33 ; CHECK: f1:
None ; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a,+t2xtpk | FileCheck %s
0 ; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7,+t2xtpk | FileCheck %s
11
22 define i32 @f1(i32 %a) {
33 ; CHECK: f1:
None ; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7a,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM
1 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7a -show-mc-encoding | FileCheck %s -check-prefix=T2
0 ; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM
1 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7 -show-mc-encoding | FileCheck %s -check-prefix=T2
22 ; rdar://8924681
33
44 define void @t1(i8* %ptr) nounwind {