llvm.org GIT mirror llvm / 399df14
[ARM] Minor refactoring to improve readability. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249454 91177308-0d34-0410-b5e6-96231b3b80d8 Chad Rosier 4 years ago
1 changed file(s) with 14 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
98349834 /// vcvt.s32.f32 d16, d16
98359835 /// becomes:
98369836 /// vcvt.s32.f32 d16, d16, #3
9837 static SDValue PerformVCVTCombine(SDNode *N,
9838 TargetLowering::DAGCombinerInfo &DCI,
9837 static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG,
98399838 const ARMSubtarget *Subtarget) {
9840 SelectionDAG &DAG = DCI.DAG;
9839 if (!Subtarget->hasNEON())
9840 return SDValue();
9841
98419842 SDValue Op = N->getOperand(0);
9842
9843 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
9844 Op.getOpcode() != ISD::FMUL)
9843 if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL)
98459844 return SDValue();
98469845
98479846 uint64_t C;
98899888 /// vdiv.f32 d16, d17, d16
98909889 /// becomes:
98919890 /// vcvt.f32.s32 d16, d16, #3
9892 static SDValue PerformVDIVCombine(SDNode *N,
9893 TargetLowering::DAGCombinerInfo &DCI,
9891 static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG,
98949892 const ARMSubtarget *Subtarget) {
9895 SelectionDAG &DAG = DCI.DAG;
9893 if (!Subtarget->hasNEON())
9894 return SDValue();
9895
98969896 SDValue Op = N->getOperand(0);
98979897 unsigned OpOpcode = Op.getNode()->getOpcode();
9898
9899 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
9898 if (!N->getValueType(0).isVector() ||
99009899 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
99019900 return SDValue();
99029901
1031410313 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
1031510314 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
1031610315 case ISD::FP_TO_SINT:
10317 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
10318 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
10316 case ISD::FP_TO_UINT:
10317 return PerformVCVTCombine(N, DCI.DAG, Subtarget);
10318 case ISD::FDIV:
10319 return PerformVDIVCombine(N, DCI.DAG, Subtarget);
1031910320 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
1032010321 case ISD::SHL:
1032110322 case ISD::SRA: