llvm.org GIT mirror llvm / 397fc48
Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
30 changed file(s) with 73 addition(s) and 49 deletion(s). Raw diff Collapse all Expand all
5656 /// class constraint for OpNum, or NULL.
5757 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
5858 unsigned OpNum,
59 const TargetRegisterInfo *TRI) const;
59 const TargetRegisterInfo *TRI,
60 const MachineFunction &MF) const;
6061
6162 /// isTriviallyReMaterializable - Return true if the instruction is trivially
6263 /// rematerializable, meaning it has no side effects and requires no operands
514514 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
515515 /// values. If a target supports multiple different pointer register classes,
516516 /// kind specifies which one is indicated.
517 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
517 virtual const TargetRegisterClass *
518 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
518519 llvm_unreachable("Target didn't implement getPointerRegClass!");
519520 }
520521
403403 // Note register reference...
404404 const TargetRegisterClass *RC = NULL;
405405 if (i < MI->getDesc().getNumOperands())
406 RC = TII->getRegClass(MI->getDesc(), i, TRI);
406 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
407407 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
408408 RegRefs.insert(std::make_pair(Reg, RR));
409409 }
478478 // Note register reference...
479479 const TargetRegisterClass *RC = NULL;
480480 if (i < MI->getDesc().getNumOperands())
481 RC = TII->getRegClass(MI->getDesc(), i, TRI);
481 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
482482 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
483483 RegRefs.insert(std::make_pair(Reg, RR));
484484 }
207207 const TargetRegisterClass *NewRC = 0;
208208
209209 if (i < MI->getDesc().getNumOperands())
210 NewRC = TII->getRegClass(MI->getDesc(), i, TRI);
210 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
211211
212212 // For now, only allow the register to be changed if its register
213213 // class is consistent across all uses.
307307
308308 const TargetRegisterClass *NewRC = 0;
309309 if (i < MI->getDesc().getNumOperands())
310 NewRC = TII->getRegClass(MI->getDesc(), i, TRI);
310 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
311311
312312 // For now, only allow the register to be changed if its register
313313 // class is consistent across all uses.
313313 // No previously defined register was in range, so create a
314314 // new one.
315315 int64_t InstrOffset = TRI->getFrameIndexInstrOffset(MI, idx);
316 const TargetRegisterClass *RC = TRI->getPointerRegClass();
316 const MachineFunction *MF = MI->getParent()->getParent();
317 const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF);
317318 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
318319
319320 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
941941 MachineInstr::getRegClassConstraint(unsigned OpIdx,
942942 const TargetInstrInfo *TII,
943943 const TargetRegisterInfo *TRI) const {
944 assert(getParent() && "Can't have an MBB reference here!");
945 assert(getParent()->getParent() && "Can't have an MF reference here!");
946 const MachineFunction &MF = *getParent()->getParent();
947
944948 // Most opcodes have fixed constraints in their MCInstrDesc.
945949 if (!isInlineAsm())
946 return TII->getRegClass(getDesc(), OpIdx, TRI);
950 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
947951
948952 if (!getOperand(OpIdx).isReg())
949953 return NULL;
965969
966970 // Assume that all registers in a memory operand are pointers.
967971 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
968 return TRI->getPointerRegClass();
972 return TRI->getPointerRegClass(MF);
969973
970974 return NULL;
971975 }
12591259 if (NewOpc == 0) return 0;
12601260 const MCInstrDesc &MID = TII->get(NewOpc);
12611261 if (MID.getNumDefs() != 1) return 0;
1262 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI);
1262 MachineFunction &MF = *MI->getParent()->getParent();
1263 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF);
12631264 // Ok, we're unfolding. Create a temporary register and do the unfold.
12641265 unsigned Reg = MRI->createVirtualRegister(RC);
12651266
1266 MachineFunction &MF = *MI->getParent()->getParent();
12671267 SmallVector NewMIs;
12681268 bool Success =
12691269 TII->unfoldMemoryOperand(MF, MI, Reg,
671671 report("Illegal subregister index for physical register", MO, MONum);
672672 return;
673673 }
674 if (const TargetRegisterClass *DRC = TII->getRegClass(MCID,MONum,TRI)) {
674 if (const TargetRegisterClass *DRC =
675 TII->getRegClass(MCID, MONum, TRI, *MF)) {
675676 if (!DRC->contains(Reg)) {
676677 report("Illegal physical register for instruction", MO, MONum);
677678 *OS << TRI->getName(Reg) << " is not a "
697698 return;
698699 }
699700 }
700 if (const TargetRegisterClass *DRC = TII->getRegClass(MCID,MONum,TRI)) {
701 if (const TargetRegisterClass *DRC =
702 TII->getRegClass(MCID, MONum, TRI, *MF)) {
701703 if (SubIdx) {
702704 const TargetRegisterClass *SuperRC =
703705 TRI->getLargestLegalSuperClass(RC);
13561358 }
13571359 }
13581360 }
1359
778778 // Make sure the copy destination register class fits the instruction
779779 // definition register class. The mismatch can happen as a result of earlier
780780 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
781 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI);
781 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF);
782782 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
783783 if (MRI->getRegClass(DstReg) != RC)
784784 return false;
115115 const TargetRegisterClass *RC = 0;
116116 if (i+II.getNumDefs() < II.getNumOperands()) {
117117 RC = TRI->getAllocatableClass(
118 TII->getRegClass(II, i+II.getNumDefs(), TRI));
118 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
119119 }
120120 if (!UseRC)
121121 UseRC = RC;
198198 // register instead of creating a new vreg.
199199 unsigned VRBase = 0;
200200 const TargetRegisterClass *RC =
201 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI));
201 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
202202 if (II.OpInfo[i].isOptionalDef()) {
203203 // Optional def must be a physical register.
204204 unsigned NumResults = CountResults(Node);
295295 if (II) {
296296 const TargetRegisterClass *DstRC = 0;
297297 if (IIOpNum < II->getNumOperands())
298 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI));
298 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
299299 assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
300300 "Don't have operand info for this instruction!");
301301 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
265265 const TargetLowering *TLI,
266266 const TargetInstrInfo *TII,
267267 const TargetRegisterInfo *TRI,
268 unsigned &RegClass, unsigned &Cost) {
268 unsigned &RegClass, unsigned &Cost,
269 const MachineFunction &MF) {
269270 EVT VT = RegDefPos.GetValue();
270271
271272 // Special handling for untyped values. These values can only come from
284285
285286 unsigned Idx = RegDefPos.GetIdx();
286287 const MCInstrDesc Desc = TII->get(Opcode);
287 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI);
288 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
288289 RegClass = RC->getID();
289290 // FIXME: Cost arbitrarily set to 1 because there doesn't seem to be a
290291 // better way to determine it.
19191920 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
19201921 RegDefPos.IsValid(); RegDefPos.Advance()) {
19211922 unsigned RCId, Cost;
1922 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost);
1923 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
19231924
19241925 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
19251926 return true;
20332034 continue;
20342035
20352036 unsigned RCId, Cost;
2036 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost);
2037 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
20372038 RegPressure[RCId] += Cost;
20382039 break;
20392040 }
20482049 if (SkipRegDefs > 0)
20492050 continue;
20502051 unsigned RCId, Cost;
2051 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost);
2052 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
20522053 if (RegPressure[RCId] < Cost) {
20532054 // Register pressure tracking is imprecise. This can happen. But we try
20542055 // hard not to let it happen because it likely results in poor scheduling.
12991299 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
13001300 const TargetRegisterClass *RC =
13011301 TRI->getAllocatableClass(
1302 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI));
1302 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, MF));
13031303 unsigned Reg = MRI->createVirtualRegister(RC);
13041304 SmallVector NewMIs;
13051305 if (!TII->unfoldMemoryOperand(MF, &MI, Reg,
258258 }
259259
260260 const TargetRegisterClass *
261 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
261 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
262 const {
262263 return &ARM::GPRRegClass;
263264 }
264265
938939
939940 const MCInstrDesc &MCID = TII.get(ADDriOpc);
940941 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
941 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this));
942 const MachineFunction &MF = *MBB->getParent();
943 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
942944
943945 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
944946 .addFrameIndex(FrameIdx).addImm(Offset));
108108 SmallVectorImpl &SubIndices,
109109 unsigned &NewSubIdx) const;
110110
111 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
111 const TargetRegisterClass*
112 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
112113 const TargetRegisterClass*
113114 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
114115
17361736 Ops.pop_back();
17371737
17381738 const MCInstrDesc &MCID = TII->get(NewOpc);
1739 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI);
1739 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF);
17401740 MRI->constrainRegClass(EvenReg, TRC);
17411741 MRI->constrainRegClass(OddReg, TRC);
17421742
219219
220220 const MCInstrDesc &MCID1 = TII->get(MulOpc);
221221 const MCInstrDesc &MCID2 = TII->get(AddSubOpc);
222 unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(MCID1, 0, TRI));
222 const MachineFunction &MF = *MI->getParent()->getParent();
223 unsigned TmpReg = MRI->createVirtualRegister(
224 TII->getRegClass(MCID1, 0, TRI, MF));
223225
224226 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
225227 .addReg(Src1Reg, getKillRegState(Src1Kill))
5353 }
5454
5555 const TargetRegisterClass *
56 Thumb1RegisterInfo::getPointerRegClass(unsigned Kind) const {
56 Thumb1RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
57 const {
5758 return &ARM::tGPRRegClass;
5859 }
5960
2929 const TargetRegisterClass*
3030 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
3131
32 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
32 const TargetRegisterClass*
33 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
3334
3435 /// emitLoadConstPool - Emits a load from constpool to materialize the
3536 /// specified immediate.
192192 /// getPointerRegClass - Return the register class to use to hold pointers.
193193 /// This is used for addressing modes.
194194 const TargetRegisterClass *
195 SPURegisterInfo::getPointerRegClass(unsigned Kind) const {
195 SPURegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
196 const {
196197 return &SPU::R32CRegClass;
197198 }
198199
4545 /// getPointerRegClass - Return the register class to use to hold pointers.
4646 /// This is used for addressing modes.
4747 virtual const TargetRegisterClass *
48 getPointerRegClass(unsigned Kind = 0) const;
48 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
4949
5050 /// After allocating this many registers, the allocator should feel
5151 /// register pressure. The value is a somewhat random guess, based on the
11271127 // For immediates, lower it.
11281128 for (unsigned i = 1; i < N->getNumOperands(); ++i) {
11291129 SDNode *Arg = N->getOperand(i).getNode();
1130 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI);
1130 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI, *MF);
11311131
11321132 if (RC == &Hexagon::IntRegsRegClass ||
11331133 RC == &Hexagon::DoubleRegsRegClass) {
27952795 // first operand is always the result
27962796
27972797 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2798 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI);
2798 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
27992799
28002800 // if there is already an store in the packet, no can do new value store
28012801 // Arch Spec 3.4.4.2.
9595 }
9696
9797 const TargetRegisterClass *
98 MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
98 MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
99 const {
99100 return &MSP430::GR16RegClass;
100101 }
101102
3838 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
3939
4040 BitVector getReservedRegs(const MachineFunction &MF) const;
41 const TargetRegisterClass* getPointerRegClass(unsigned Kind = 0) const;
41 const TargetRegisterClass*
42 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
4243
4344 void eliminateCallFramePseudoInstr(MachineFunction &MF,
4445 MachineBasicBlock &MBB,
9797 /// getPointerRegClass - Return the register class to use to hold pointers.
9898 /// This is used for addressing modes.
9999 const TargetRegisterClass *
100 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const {
100 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
101 const {
101102 if (Subtarget.isPPC64())
102103 return &PPC::G8RCRegClass;
103104 return &PPC::GPRCRegClass;
3434
3535 /// getPointerRegClass - Return the register class to use to hold pointers.
3636 /// This is used for addressing modes.
37 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const;
37 virtual const TargetRegisterClass *
38 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const;
3839
3940 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
4041 MachineFunction &MF) const;
2727
2828 const TargetRegisterClass*
2929 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
30 const TargetRegisterInfo *TRI) const {
30 const TargetRegisterInfo *TRI,
31 const MachineFunction &MF) const {
3132 if (OpNum >= MCID.getNumOperands())
3233 return 0;
3334
3435 short RegClass = MCID.OpInfo[OpNum].RegClass;
3536 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
36 return TRI->getPointerRegClass(RegClass);
37 return TRI->getPointerRegClass(MF, RegClass);
3738
3839 // Instructions like INSERT_SUBREG do not have fixed register classes.
3940 if (RegClass < 0)
28102810 return NULL;
28112811 bool NarrowToMOV32rm = false;
28122812 if (Size) {
2813 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize();
2813 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
28142814 if (Size < RCSize) {
28152815 // Check if it's safe to fold the load. If the size of the object is
28162816 // narrower than the load width, then it's not.
32033203 UnfoldStore &= FoldedStore;
32043204
32053205 const MCInstrDesc &MCID = get(Opc);
3206 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
3206 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
32073207 if (!MI->hasOneMemOperand() &&
32083208 RC == &X86::VR128RegClass &&
32093209 !TM.getSubtarget().isUnalignedMemAccessFast())
32983298
32993299 // Emit the store instruction.
33003300 if (UnfoldStore) {
3301 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI);
3301 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
33023302 std::pair
33033303 MachineInstr::mmo_iterator> MMOs =
33043304 MF.extractStoreMemRefs(MI->memoperands_begin(),
33243324 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
33253325 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
33263326 const MCInstrDesc &MCID = get(Opc);
3327 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
3327 MachineFunction &MF = DAG.getMachineFunction();
3328 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
33283329 unsigned NumDefs = MCID.NumDefs;
33293330 std::vector AddrOps;
33303331 std::vector BeforeOps;
33453346
33463347 // Emit the load instruction.
33473348 SDNode *Load = 0;
3348 MachineFunction &MF = DAG.getMachineFunction();
33493349 if (FoldedLoad) {
33503350 EVT VT = *RC->vt_begin();
33513351 std::pair
33723372 std::vector VTs;
33733373 const TargetRegisterClass *DstRC = 0;
33743374 if (MCID.getNumDefs() > 0) {
3375 DstRC = getRegClass(MCID, 0, &RI);
3375 DstRC = getRegClass(MCID, 0, &RI, MF);
33763376 VTs.push_back(*DstRC->vt_begin());
33773377 }
33783378 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
180180 }
181181
182182 const TargetRegisterClass *
183 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
183 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
184 const {
184185 switch (Kind) {
185186 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
186187 case 0: // Normal GPRs.
8282
8383 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
8484 /// values.
85 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
85 const TargetRegisterClass *
86 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
8687
8788 /// getCrossCopyRegClass - Returns a legal register class to copy a register
8889 /// in the specified class to or from. Returns NULL if it is possible to copy