llvm.org GIT mirror llvm / 38e6f73
Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199295 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 6 years ago
2 changed file(s) with 20 addition(s) and 25 deletion(s). Raw diff Collapse all Expand all
231231 Form = byteFromRec(Rec, "FormBits");
232232
233233 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
234 HasOpSize16Prefix = Rec->getValueAsBit("hasOpSize16Prefix");
234235 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
235236 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
236237 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
253254
254255 Operands = &insn.Operands.OperandList;
255256
256 IsSSE = ((HasOpSizePrefix || Prefix == X86Local::PD ||
257 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
258 (Name.find("16") == Name.npos)) ||
259 (Name.find("CRC32") != Name.npos);
260257 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
261258
262259 // Check for 64-bit inst which does not require REX
557554 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
558555 HasOpSizePrefix);
559556 Spec->operands[operandIndex].type = typeFromString(typeName,
560 IsSSE,
561557 HasREX_WPrefix,
562 HasOpSizePrefix);
558 HasOpSizePrefix,
559 HasOpSize16Prefix);
563560
564561 ++operandIndex;
565562 ++physicalOperandIndex;
11631160
11641161 #define TYPE(str, type) if (s == str) return type;
11651162 OperandType RecognizableInstr::typeFromString(const std::string &s,
1166 bool isSSE,
11671163 bool hasREX_WPrefix,
1168 bool hasOpSizePrefix) {
1169 if (isSSE) {
1170 // For SSE instructions, we ignore the OpSize prefix and force operand
1171 // sizes.
1172 TYPE("GR16", TYPE_R16)
1173 TYPE("GR32", TYPE_R32)
1174 TYPE("GR64", TYPE_R64)
1175 }
1164 bool hasOpSizePrefix,
1165 bool hasOpSize16Prefix) {
11761166 if(hasREX_WPrefix) {
11771167 // For instructions with a REX_W prefix, a declared 32-bit register encoding
11781168 // is special.
11791169 TYPE("GR32", TYPE_R32)
11801170 }
1181 if(!hasOpSizePrefix) {
1182 // For instructions without an OpSize prefix, a declared 16-bit register or
1171 if(hasOpSizePrefix) {
1172 // For instructions with an OpSize prefix, a declared 16-bit register or
11831173 // immediate encoding is special.
1184 TYPE("GR16", TYPE_R16)
1185 TYPE("i16imm", TYPE_IMM16)
1174 TYPE("GR16", TYPE_Rv)
1175 TYPE("i16imm", TYPE_IMMv)
1176 }
1177 if(hasOpSize16Prefix) {
1178 // For instructions with an OpSize16 prefix, a declared 32-bit register or
1179 // immediate encoding is special.
1180 TYPE("GR32", TYPE_Rv)
11861181 }
11871182 TYPE("i16mem", TYPE_Mv)
1188 TYPE("i16imm", TYPE_IMMv)
1183 TYPE("i16imm", TYPE_IMM16)
11891184 TYPE("i16i8imm", TYPE_IMMv)
1190 TYPE("GR16", TYPE_Rv)
1185 TYPE("GR16", TYPE_R16)
11911186 TYPE("i32mem", TYPE_Mv)
11921187 TYPE("i32imm", TYPE_IMMv)
11931188 TYPE("i32i8imm", TYPE_IMM32)
11941189 TYPE("u32u8imm", TYPE_IMM32)
1195 TYPE("GR32", TYPE_Rv)
1190 TYPE("GR32", TYPE_R32)
11961191 TYPE("GR32orGR64", TYPE_R32)
11971192 TYPE("i64mem", TYPE_Mv)
11981193 TYPE("i64i32imm", TYPE_IMM64)
4545 uint8_t Form;
4646 /// The hasOpSizePrefix field from the record
4747 bool HasOpSizePrefix;
48 /// The hasOpSize16Prefix field from the record
49 bool HasOpSize16Prefix;
4850 /// The hasAdSizePrefix field from the record
4951 bool HasAdSizePrefix;
5052 /// The hasREX_WPrefix field from the record
8890 std::string Name;
8991 /// The AT&T AsmString for the instruction
9092 std::string AsmString;
91
92 /// Indicates whether the instruction is SSE
93 bool IsSSE;
93
9494 /// Indicates whether the instruction should be emitted into the decode
9595 /// tables; regardless, it will be emitted into the instruction info table
9696 bool ShouldBeEmitted;