llvm.org GIT mirror llvm / 38c6ff6
Improve llvm-mc disassembler mode and refactor ARM tests to use it This allows "llvm-mc -disassemble" to accept two new features: + Using comma as a byte separator + Grouping bytes with '[' and ']' pairs. The behaviour outside a [...] group is unchanged. But within the group once llvm-mc encounters a true error, it stops rather than trying to resynchronise the stream at the next byte. This is more useful for disassembly tests, where we have an almost-instruction in mind and don't care what the misaligned interpretation would be. Particularly if it means llvm-mc won't actually see the next intended almost-instruction. As a side effect, this means llvm-mc can disassemble its own -show-encoding output if copy-pasted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186661 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 6 years ago
64 changed file(s) with 1034 addition(s) and 625 deletion(s). Raw diff Collapse all Expand all
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test/MC/Disassembler/ARM/invalid-BFI-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # if d == 15 then UNPREDICTABLE;
9 0x16 0xf0 0xcf 0xe7
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test/MC/Disassembler/ARM/invalid-CDP2-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm 2>&1 | FileCheck %s
1
2 # CHECK: invalid instruction encoding
3 0xe0 0x6a 0x0c 0xfe
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test/MC/Disassembler/ARM/invalid-CPS-arm.txt less more
None # CPS: various encodings that are ambiguous with other instructions
1
2 # RUN: echo "0x9f 0xff 0x4e 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
3 # RUN: echo "0x80 0x80 0x2c 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
4 # RUN: echo "0xce 0x3f 0x28 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
5 # RUN: echo "0x80 0x00 0x20 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
6 # RUN: echo "0xa0 0x00 0x00 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
7
8 # CHECK: invalid instruction encoding
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test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # invalid imod value (0b01)
3 0xc0 0x67 0x4 0xf1
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test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
1
2 # invalid (imod, M, iflags) combination
3 0x93 0x00 0x02 0xf1
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test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
1
2 # CBZ / CBNZ not allowed in IT block.
3
4 0xdb 0xbf 0x42 0xbb
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test/MC/Disassembler/ARM/invalid-IT-thumb.txt less more
None # CHECK-UNPRED: potentially undefined instruction encoding
1 # CHECK-UNDEF: invalid instruction encoding
2
3 # RUN: echo "0xff 0xbf 0x6b 0x80 0x00 0x75" | llvm-mc -disassemble -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK-UNPRED
4
5 # mask = 0
6 # RUN: echo "0x50 0xbf 0x00 0x00" | llvm-mc -disassemble -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK-UNDEF
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test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=0 Name=PHI Format=(42)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined.
9 0x92 0xb4 0x1f 0xdc
10
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test/MC/Disassembler/ARM/invalid-LDM-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
1
2 # Writeback is not allowed is Rn is in the target register list.
3
4 0xb4 0xe8 0x34 0x04
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test/MC/Disassembler/ARM/invalid-LDR-thumb.txt less more
None # invalid LDRSHs Rt=PC
1 # RUN: echo "0x30 0xf9 0x00 0xf0" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
2
3 # invalid LDRSHi8 Rt=PC
4 # RUN: echo "0x30 0xf9 0x00 0xfc" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
5
6 # invalid LDRSHi12 Rt=PC
7 # RUN: echo "0xb0 0xf9 0x00 0xf0" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
8
9 # CHECK: invalid instruction encoding
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test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
1
2 # Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # if wback && (n == 15 || n == t) then UNPREDICTABLE
9 0x05 0x70 0xd7 0xe6
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test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined"
1
2 # Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # A8.6.66 LDRD (immediate)
9 # if Rn = '1111' then SEE LDRD (literal)
10 # A8.6.67 LDRD (literal)
11 # Inst{21} = 0
12 0xff 0xe9 0x0 0xeb
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test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # LDR_PRE/POST has encoding Inst{4} = 0.
3 0xde 0x69 0x18 0x46
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test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
1
2 # Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # if m == 15 then UNPREDICTABLE
9 0x8f 0x60 0xb7 0xe7
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test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # LDR (register) has encoding Inst{4} = 0.
3 0xba 0xae 0x9f 0x57
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test/MC/Disassembler/ARM/invalid-MCR-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C
9 0x1b 0x1b 0xa0 0x2e
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test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # if d == 15 then UNPREDICTABLE
9 0x00 0xf0 0x41 0xe3
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test/MC/Disassembler/ARM/invalid-MOVr-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=0 Name=PHI Format=(42)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0|
6 # -------------------------------------------------------------------------------------------------
7 # To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
8 # The instruction is UNPREDICTABLE, and is not a valid intruction.
9 #
10 # See also
11 # A8.6.97 MOV (register)
12 0x2 0xd0 0xbc 0xf1
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test/MC/Disassembler/ARM/invalid-MOVs-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=0 Name=PHI Format=(42)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0|
6 # -------------------------------------------------------------------------------------------------
7 # To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
8 # The instruction is UNPREDICTABLE, and is not a valid intruction.
9 #
10 # See also
11 # A8.6.88 LSL (immediate)
12 # A8.6.98 MOV (shifted register), and
13 # I.1 Instruction encoding diagrams and pseudocode
14 0x2 0xd1 0xbc 0xf1
15
16
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test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s
1
2 # CHECK: invalid instruction encoding
3 0x00 0x1a 0x50 0xfc
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test/MC/Disassembler/ARM/invalid-MSRi-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
9 # The hints instructions have more specific encodings, so if mask == 0,
10 # we should reject this as an invalid instruction.
11 0xa7 0xf1 0x20 0x3
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test/MC/Disassembler/ARM/invalid-NEON-thumb.txt less more
None # VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110)
1
2 # VMOV
3 # RUN: echo "0x00 0xde 0x10 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
4
5 # VDUP
6 # RUN: echo "0xff 0xde 0xf0 0xfb" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
7
8 # CHECK: invalid instruction encoding
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test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction
9 # A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction
10 0x32 0xb1 0x99 0xf8
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test/MC/Disassembler/ARM/invalid-SBFX-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # if d == 15 || n == 15 then UNPREDICTABLE;
9 0x5f 0x54 0xa7 0xe7
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-11
test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # A8.6.167
9 # if d == 15 || n == 15 | m == 15 then UNPREDICTABLE
10 0x1b 0x68 0xf 0x97
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test/MC/Disassembler/ARM/invalid-SRS-arm.txt less more
None # Opcode=0 Name=PHI Format=(42)
1 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2 # -------------------------------------------------------------------------------------------------
3 # | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1|
4 # -------------------------------------------------------------------------------------------------
5 # Unknown format
6 #
7 # B6.1.10 SRS
8 # Inst{19-8} = 0xd05
9 # Inst{7-5} = 0b000
10 # RUN: echo "0x83 0x1c 0xc5 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
11
12 # RUN: echo "0x00 0x00 0x20 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
13 # RUN: echo "0xff 0xff 0xaf 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
14 # RUN: echo "0x13 0x00 0xa0 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
15
16 # CHECK: invalid instruction encoding
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test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # if BitCount(registers) < 1 then UNPREDICTABLE
9 0x00 0xc7
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-37
test/MC/Disassembler/ARM/invalid-STR-thumb.txt less more
None # invalid STRi12 Rn=PC
1 # RUN: echo "0xcf 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
2
3 # invalid STRi8 Rn=PC
4 # RUN: echo "0x4f 0xf8 0x00 0x0c" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
5
6 # invalid STRs Rn=PC
7 # RUN: echo "0x4f 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
8
9 # invalid STRBi12 Rn=PC
10 # RUN: echo "0x0f 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
11
12 # invalid STRBi8 Rn=PC
13 # RUN: echo "0x0f 0xf8 0x00 0x0c" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
14
15 # invalid STRBs Rn=PC
16 # RUN: echo "0x0f 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
17
18 # invalid STRHi12 Rn=PC
19 # RUN: echo "0xaf 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
20
21 # invalid STRHi8 Rn=PC
22 # RUN: echo "0x2f 0xf8 0x00 0x0c" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
23
24 # invalid STRHs Rn=PC
25 # RUN: echo "0x2f 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
26
27 # invalid STRBT Rn=PC
28 # RUN: echo "0x0f 0xf8 0x00 0x0e" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
29
30 # invalid STRHT Rn=PC
31 # RUN: echo "0x2f 0xf8 0x00 0x0e" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
32
33 # invalid STRT Rn=PC
34 # RUN: echo "0x4f 0xf8 0x00 0x0e" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
35
36 # CHECK: invalid instruction encoding
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test/MC/Disassembler/ARM/invalid-SXTB-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # A8.6.223 SXTB
9 # if d == 15 || m == 15 then UNPREDICTABLE;
10 0x75 0xf4 0xaf 0xe6
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test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # A8.6.244 UMAAL
9 # if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
10 0x98 0xbf 0x4f 0xf0
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-8
test/MC/Disassembler/ARM/invalid-VCVT-arm.txt less more
None # A8.8.307: VCVT (between floating-point and fixed-point, AdvSIMD)
1 # imm6=0b0xxxxx -> UNDEFINED
2
3 # RUN: echo "0x1e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s
4
5 # RUN: echo "0x3e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s
6
7 # CHECK: invalid instruction encoding
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test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | grep "invalid instruction encoding"
1
2 # invalid imm4 value (0b1xxx)
3 # A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
4 0x8f 0xf9 0xf7 0xf2
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-9
test/MC/Disassembler/ARM/invalid-VFP-thumb.txt less more
None # VFP instructions with invalid predicate bits (pred != 0b1110)
1
2 # VABS
3 # RUN: echo "0x40 0xde 0x00 0x0a" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
4
5 # VMLA
6 # RUN: echo "0xf0 0xde 0xe0 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
7
8 # CHECK: invalid instruction encoding
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test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
1
2 # Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # 'a' == 1 and data_size == 8 is invalid
9 0x3d 0x3c 0xa0 0xf4
10 # CHECK: invalid instruction encoding
+0
-4
test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt less more
None # RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
1
2 0xa0 0xf9 0x10 0x08
3 # CHECK: invalid instruction encoding
+0
-11
test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # A8.6.315 VLD3 (single 3-element structure to all lanes)
9 # The a bit must be encoded as 0.
10 0xa2 0xf9 0x92 0x2e
+0
-4
test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt less more
None # RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
1
2 0xa0 0xf9 0xc0 0x0f
3 # CHECK: invalid instruction encoding
+0
-4
test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt less more
None # RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
1
2 0xa0 0xf9 0x30 0x0b
3 # CHECK: invalid instruction encoding
+0
-4
test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # core registers out of range
3 0xa5 0xba 0x72 0xed
+0
-62
test/MC/Disassembler/ARM/invalid-VLDST-arm.txt less more
None # VST1 multi-element, type == 0b0111, align == 0b10 -> undefined
1 # RUN: echo "0xaf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
2
3 # VST1 multi-element, type == 0b0111, align == 0b11 -> undefined
4 # RUN: echo "0xbf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
5
6 # VST1 multi-element, type == 0b1010, align == 0b11 -> undefined
7 # RUN: echo "0xbf 0x8a 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
8
9 # VST1 multi-element, type == 0b0110, align == 0b10 -> undefined
10 # RUN: echo "0xaf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
11
12 # VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
13 # RUN: echo "0xbf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
14
15 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
16 # RUN: echo "0x4f 0xa8 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
17
18 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
19 # RUN: echo "0x4f 0xa9 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
20
21 # VST3 multi-element, size = 0b11 -> undefined
22 # RUN: echo "0xbf 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
23
24 # VST3 multi-element, align = 0b10 -> undefined
25 # RUN: echo "0x6f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
26
27 # VST3 multi-element, align = 0b11 -> undefined
28 # RUN: echo "0x7f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
29
30 # VST4 multi-element, size = 0b11 -> undefined
31 # RUN: echo "0xcf 0x50 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
32
33 # VLD1 multi-element, type=0b1010 align=0b11
34 # RUN: echo "0x24 0xf9 0xbf 0x8a" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
35
36 # VLD1 multi-element type=0b0111 align=0b1x
37 # RUN: echo "0x24 0xf9 0xbf 0x87" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
38
39 # VLD1 multi-element type=0b0010 align=0b1x
40 # RUN: echo "0x24 0xf9 0xbf 0x86" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
41
42 # VLD2 multi-element size=0b11
43 # RUN: echo "0x60 0xf9 0xcf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
44
45 # VLD2 multi-element type=0b1111 align=0b11
46 # RUN: echo "0x60 0xf9 0xbf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
47
48 # VLD2 multi-element type=0b1001 align=0b11
49 # RUN: echo "0x60 0xf9 0xbf 0x09" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
50
51 # VLD3 multi-element size=0b11
52 # RUN: echo "0x60 0xf9 0x7f 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
53
54 # VLD3 multi-element align=0b1x
55 # RUN: echo "0x60 0xf9 0xcf 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
56
57 # VLD4 multi-element size=0b11
58 # RUN: echo "0x60 0xf9 0xcd 0x11" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
59
60 # CHECK: invalid instruction encoding
61
+0
-7
test/MC/Disassembler/ARM/invalid-VMOV-arm.txt less more
None # VMOV cmode=0b1111 op=1
1 # RUN: echo "0x70 0xef 0xc7 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
2
3 # VMOV cmode=0b1111 op=1
4 # RUN: echo "0x30 0x0f 0x80 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
5
6 # CHECK: invalid instruction encoding
+0
-11
test/MC/Disassembler/ARM/invalid-VQADD-arm.txt less more
None # RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
1
2 # Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # Qm -> bit[0] == 0, otherwise UNDEFINED
9 0xdb 0xe0 0x40 0xf2
10 # CHECK: invalid instruction encoding
+0
-4
test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt less more
None # RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
1
2 0x80 0xf9 0x10 0x08
3 # CHECK: invalid instruction encoding
+0
-13
test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # A8.6.391 VST1 (multiple single elements)
9 # This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128]
10 # But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if
11 # contains two or four registers. rdar://11220250
12 0x00 0xf9 0x2f 0x06
+0
-18
test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt less more
None # Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
1 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2 # -------------------------------------------------------------------------------------------------
3 # | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
4 # -------------------------------------------------------------------------------------------------
5 #
6 # A8.6.393 VST2 (multiple 2-element structures)
7 # type == '1001' and align == '11' ==> UNDEFINED
8 # RUN: echo "0xb3 0x09 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
9
10 # size == '11' ==> UNDEFINED
11 # RUN: echo "0xc3 0x08 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
12
13 # type == '1000' and align == '11' ==> UNDEFINED
14 # RUN: echo "0xb3 0x08 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
15
16 # CHECK: invalid instruction encoding
17
+0
-4
test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt less more
None # RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
1
2 0x80 0xf9 0x30 0x0b
3 # CHECK: invalid instruction encoding
0 # RUN: llvm-mc -disassemble %s -mcpu cortex-a8 -triple armv7 2>&1 | FileCheck %s
1
2 # This file is checking ARMv7 encodings which are globally invalid, usually due
3 # to the constraints of the instructions not being met. For example invalid
4 # combinations of registers.
5
6
7 #------------------------------------------------------------------------------
8 # Undefined encodings for bfi
9 #------------------------------------------------------------------------------
10
11 # Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4)
12 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
13 # -------------------------------------------------------------------------------------------------
14 # | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0|
15 # -------------------------------------------------------------------------------------------------
16 #
17 # if d == 15 then UNPREDICTABLE;
18 [0x16 0xf0 0xcf 0xe7]
19 # CHECK: potentially undefined instruction encoding
20 # CHECK-NEXT: [0x16 0xf0 0xcf 0xe7]
21
22 #------------------------------------------------------------------------------
23 # Undefined encodings for cdp2
24 #------------------------------------------------------------------------------
25
26 [0xe0 0x6a 0x0c 0xfe]
27 # CHECK: invalid instruction encoding
28 # CHECK-NEXT: [0xe0 0x6a 0x0c 0xfe]
29
30
31 #------------------------------------------------------------------------------
32 # Undefined encodings for cps*
33 #------------------------------------------------------------------------------
34
35 # invalid imod value (0b01)
36 [0xc0 0x67 0x4 0xf1]
37 # CHECK: invalid instruction encoding
38 # CHECK-NEXT: [0xc0 0x67 0x4 0xf1]
39
40 # invalid (imod, M, iflags) combination
41 [0x93 0x00 0x02 0xf1]
42 # CHECK: potentially undefined instruction encoding
43 # CHECK-NEXT: [0x93 0x00 0x02 0xf1]
44
45 # CPS: various encodings that are ambiguous with other instructions
46 [0x9f 0xff 0x4e 0xf1]
47 # CHECK: invalid instruction encoding
48 # CHECK-NEXT: [0x9f 0xff 0x4e 0xf1]
49
50 [0x80 0x80 0x2c 0xf1]
51 # CHECK: invalid instruction encoding
52 # CHECK-NEXT: [0x80 0x80 0x2c 0xf1]
53
54 [0xce 0x3f 0x28 0xf1]
55 # CHECK: invalid instruction encoding
56 # CHECK-NEXT: [0xce 0x3f 0x28 0xf1]
57
58 [0x80 0x00 0x20 0xf1]
59 # CHECK: invalid instruction encoding
60 # CHECK-NEXT: [0x80 0x00 0x20 0xf1]
61
62 [0xa0 0x00 0x00 0xf1]
63 # CHECK: invalid instruction encoding
64 # CHECK-NEXT: [0xa0 0x00 0x00 0xf1]
65
66
67 #------------------------------------------------------------------------------
68 # Undefined encoding space for hint instructions
69 #------------------------------------------------------------------------------
70
71 [0x05 0xf0 0x20 0xe3]
72 # CHECK: invalid instruction encoding
73 # CHECK-NEXT: [0x05 0xf0 0x20 0xe3]
74
75 [0x41 0xf0 0x20 0xe3]
76 # CHECK: invalid instruction encoding
77 # CHECK-NEXT: [0x41 0xf0 0x20 0xe3]
78
79 # FIXME: is it "dbg #14" or not????
80 [0xfe 0xf0 0x20 0xe3]
81 # CHCK: invalid instruction encoding
82
83
84 #------------------------------------------------------------------------------
85 # Undefined encodings for ldc
86 #------------------------------------------------------------------------------
87
88 # Opcode=0 Name=PHI Format=(42)
89 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
90 # -------------------------------------------------------------------------------------------------
91 # | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0|
92 # -------------------------------------------------------------------------------------------------
93 #
94 # The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined.
95
96 [0x92 0xb4 0x1f 0xdc]
97 # CHECK: invalid instruction encoding
98 # CHECK-NEXT: [0x92 0xb4 0x1f 0xdc]
99
100
101 #------------------------------------------------------------------------------
102 # Undefined encodings for ldm
103 #------------------------------------------------------------------------------
104
105 # Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10)
106 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
107 # -------------------------------------------------------------------------------------------------
108 # | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0|
109 # -------------------------------------------------------------------------------------------------
110 #
111 # B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction
112 # A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction
113
114 [0x32 0xb1 0x99 0xf8]
115 # CHECK: invalid instruction encoding
116 # CHECK-NEXT: [0x32 0xb1 0x99 0xf8]
117
118
119 #------------------------------------------------------------------------------
120 # Undefined encodings for ldr
121 #------------------------------------------------------------------------------
122
123 # Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6)
124 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
125 # -------------------------------------------------------------------------------------------------
126 # | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1|
127 # -------------------------------------------------------------------------------------------------
128 #
129 # if m == 15 then UNPREDICTABLE
130
131 [0x8f 0x60 0xb7 0xe7]
132 # CHECK: potentially undefined instruction encoding
133 # CHECK-NEXT: [0x8f 0x60 0xb7 0xe7]
134
135 # LDR (register) has encoding Inst{4} = 0.
136 [0xba 0xae 0x9f 0x57]
137 # CHECK: invalid instruction encoding
138 # CHECK-NEXT: [0xba 0xae 0x9f 0x57]
139
140 # LDR_PRE/POST has encoding Inst{4} = 0.
141 [0xde 0x69 0x18 0x46]
142 # CHECK: invalid instruction encoding
143 # CHECK-NEXT: [0xde 0x69 0x18 0x46]
144
145 # Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6)
146 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
147 # -------------------------------------------------------------------------------------------------
148 # | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1|
149 # -------------------------------------------------------------------------------------------------
150 #
151 # if wback && (n == 15 || n == t) then UNPREDICTABLE
152 [0x05 0x70 0xd7 0xe6]
153 # CHECK: potentially undefined instruction encoding
154 # CHECK-NEXT: [0x05 0x70 0xd7 0xe6]
155
156
157
158 #------------------------------------------------------------------------------
159 # Undefined encodings for mcr
160 #------------------------------------------------------------------------------
161
162 # Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2)
163 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
164 # -------------------------------------------------------------------------------------------------
165 # | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1|
166 # -------------------------------------------------------------------------------------------------
167 #
168 # Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C
169
170 [0x1b 0x1b 0xa0 0x2e]
171 # CHECK: invalid instruction encoding
172 # CHECK-NEXT: [0x1b 0x1b 0xa0 0x2e]
173
174
175 #------------------------------------------------------------------------------
176 # Undefined encodings for mov/lsl
177 #------------------------------------------------------------------------------
178
179 # Opcode=0 Name=PHI Format=(42)
180 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
181 # -------------------------------------------------------------------------------------------------
182 # | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0|
183 # -------------------------------------------------------------------------------------------------
184 # To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
185 # The instruction is UNPREDICTABLE, and is not a valid intruction.
186 #
187 # See also
188 # A8.6.88 LSL (immediate)
189 # A8.6.98 MOV (shifted register), and
190 # I.1 Instruction encoding diagrams and pseudocode
191
192 [0x2 0xd1 0xbc 0xf1]
193 # CHECK: invalid instruction encoding
194 # CHECK-NEXT: [0x2 0xd1 0xbc 0xf1]
195
196
197 # Opcode=0 Name=PHI Format=(42)
198 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
199 # -------------------------------------------------------------------------------------------------
200 # | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0|
201 # -------------------------------------------------------------------------------------------------
202 # To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
203 # The instruction is UNPREDICTABLE, and is not a valid intruction.
204 #
205 # See also
206 # A8.6.97 MOV (register)
207
208 [0x2 0xd0 0xbc 0xf1]
209 # CHECK: invalid instruction encoding
210 # CHECK-NEXT: [0x2 0xd0 0xbc 0xf1]
211
212 # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
213 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
214 # -------------------------------------------------------------------------------------------------
215 # | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1|
216 # -------------------------------------------------------------------------------------------------
217 # A8.6.89 LSL (register): Inst{7-4} = 0b0001
218 [0x93 0x42 0xa0 0xd1]
219 # CHECK: invalid instruction encoding
220 # CHECK-NEXT: [0x93 0x42 0xa0 0xd1]
221
222 # Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4)
223 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
224 # -------------------------------------------------------------------------------------------------
225 # | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
226 # -------------------------------------------------------------------------------------------------
227 #
228 # if d == 15 then UNPREDICTABLE
229 [0x00 0xf0 0x41 0xe3]
230 # CHECK: potentially undefined instruction encoding
231 # CHECK-NEXT: [0x00 0xf0 0x41 0xe3]
232
233
234 #------------------------------------------------------------------------------
235 # Undefined encodings for mrrc2
236 #------------------------------------------------------------------------------
237
238 [0x00 0x1a 0x50 0xfc]
239 # CHECK: invalid instruction encoding
240 # CHECK-NEXT: [0x00 0x1a 0x50 0xfc]
241
242
243 #------------------------------------------------------------------------------
244 # Undefined encodings for msr (imm)
245 #------------------------------------------------------------------------------
246
247 # Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2)
248 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
249 # -------------------------------------------------------------------------------------------------
250 # | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1|
251 # -------------------------------------------------------------------------------------------------
252 #
253 # A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
254 # The hints instructions have more specific encodings, so if mask == 0,
255 # we should reject this as an invalid instruction.
256
257 [0xa7 0xf1 0x20 0x3]
258 # CHECK: invalid instruction encoding
259 # CHECK-NEXT: [0xa7 0xf1 0x20 0x3]
260
261
262 #------------------------------------------------------------------------------
263 # Undefined encodings for sbfx
264 #------------------------------------------------------------------------------
265
266 # Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4)
267 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
268 # -------------------------------------------------------------------------------------------------
269 # | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
270 # -------------------------------------------------------------------------------------------------
271 #
272 # if d == 15 || n == 15 then UNPREDICTABLE;
273
274 [0x5f 0x54 0xa7 0xe7]
275 # CHECK: potentially undefined instruction encoding
276 # CHECK-NEXT: [0x5f 0x54 0xa7 0xe7]
277
278 #------------------------------------------------------------------------------
279 # Undefined encodings for smlad
280 #------------------------------------------------------------------------------
281
282 # Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1)
283 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
284 # -------------------------------------------------------------------------------------------------
285 # | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1|
286 # -------------------------------------------------------------------------------------------------
287 #
288 # A8.6.167
289 # if d == 15 || n == 15 | m == 15 then UNPREDICTABLE
290
291 [0x1b 0x68 0xf 0x97]
292 # CHECK: potentially undefined instruction encoding
293 # CHECK-NEXT: [0x1b 0x68 0xf 0x97]
294
295
296 #------------------------------------------------------------------------------
297 # Undefined encodings for srs
298 #------------------------------------------------------------------------------
299
300 # Opcode=0 Name=PHI Format=(42)
301 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
302 # -------------------------------------------------------------------------------------------------
303 # | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1|
304 # -------------------------------------------------------------------------------------------------
305 # Unknown format
306 #
307 # B6.1.10 SRS
308 # Inst{19-8} = 0xd05
309 # Inst{7-5} = 0b000
310
311 [0x83 0x1c 0xc5 0xf8]
312 # CHECK: invalid instruction encoding
313 # CHECK-NEXT: [0x83 0x1c 0xc5 0xf8]
314
315 [0x00 0x00 0x20 0xf8]
316 # CHECK: invalid instruction encoding
317 # CHECK-NEXT: [0x00 0x00 0x20 0xf8]
318
319 [0xff 0xff 0xaf 0xf8]
320 # CHECK: invalid instruction encoding
321 # CHECK-NEXT: [0xff 0xff 0xaf 0xf8]
322
323 [0x13 0x00 0xa0 0xf8]
324 # CHECK: invalid instruction encoding
325 # CHECK-NEXT: [0x13 0x00 0xa0 0xf8]
326
327 #------------------------------------------------------------------------------
328 # Undefined encodings for sxtb
329 #------------------------------------------------------------------------------
330
331 # Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14)
332 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
333 # -------------------------------------------------------------------------------------------------
334 # | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1|
335 # -------------------------------------------------------------------------------------------------
336 #
337 # A8.6.223 SXTB
338 # if d == 15 || m == 15 then UNPREDICTABLE;
339
340 [0x75 0xf4 0xaf 0xe6]
341 # CHECK: potentially undefined instruction encoding
342 # CHECK-NEXT: [0x75 0xf4 0xaf 0xe6]
343
344 #------------------------------------------------------------------------------
345 # Undefined encodings for NEON umaal
346 #------------------------------------------------------------------------------
347
348 # Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1)
349 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
350 # -------------------------------------------------------------------------------------------------
351 # | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0|
352 # -------------------------------------------------------------------------------------------------
353 #
354 # A8.6.244 UMAAL
355 # if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
356 [0x98 0xbf 0x4f 0xf0]
357 # CHECK: invalid instruction encoding
358 # CHECK-NEXT: [0x98 0xbf 0x4f 0xf0]
359
360 #------------------------------------------------------------------------------
361 # Undefined encodings for NEON vcvt (float <-> fixed)
362 #------------------------------------------------------------------------------
363
364 # imm6=0b0xxxxx -> UNDEFINED
365 [0x1e 0xcf 0x92 0xf3]
366 # CHECK: invalid instruction encoding
367 # CHECK-NEXT: [0x1e 0xcf 0x92 0xf3]
368
369 [0x3e 0xcf 0x92 0xf3]
370 # CHECK: invalid instruction encoding
371 # CHECK-NEXT: [0x3e 0xcf 0x92 0xf3]
372
373
374 #------------------------------------------------------------------------------
375 # Undefined encodings for NEON vext
376 #------------------------------------------------------------------------------
377
378 # invalid imm4 value (0b1xxx)
379 # A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
380 [0x8f 0xf9 0xf7 0xf2]
381 # CHECK: invalid instruction encoding
382 # CHECK-NEXT: [0x8f 0xf9 0xf7 0xf2]
383
384 #------------------------------------------------------------------------------
385 # Undefined encodings for NEON vldmsdb
386 #------------------------------------------------------------------------------
387
388 # core registers out of range
389 [0xa5 0xba 0x72 0xed]
390 # CHECK: potentially undefined instruction encoding
391 # CHECK-NEXT: [0xa5 0xba 0x72 0xed]
392
393
394 #------------------------------------------------------------------------------
395 # Undefined encodings for NEON vmov
396 #------------------------------------------------------------------------------
397
398 # VMOV cmode=0b1111 op=1 is UNDEFINED
399 [0x70 0xef 0xc7 0xf3]
400 # CHECK: invalid instruction encoding
401 # CHECK-NEXT: [0x70 0xef 0xc7 0xf3]
402
403 # VMOV cmode=0b1111 op=1 is UNDEFINED
404 [0x30 0x0f 0x80 0xf3]
405 # CHECK: invalid instruction encoding
406 # CHECK-NEXT: [0x30 0x0f 0x80 0xf3]
407
408
409 #------------------------------------------------------------------------------
410 # Undefined encodings for NEON vqadd
411 #------------------------------------------------------------------------------
412
413 # Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37)
414 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
415 # -------------------------------------------------------------------------------------------------
416 # | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1|
417 # -------------------------------------------------------------------------------------------------
418 #
419 # Qm -> bit[0] == 0, otherwise UNDEFINED
420 [0xdb 0xe0 0x40 0xf2]
421 # CHECK: invalid instruction encoding
422 # CHECK-NEXT: [0xdb 0xe0 0x40 0xf2]
423
424
425 #------------------------------------------------------------------------------
426 # Undefined encodings for NEON vld/vst
427 #------------------------------------------------------------------------------
428
429 # A8.6.393 VST2 (multiple 2-element structures)
430 [0xb3 0x09 0x03 0xf4]
431 # CHECK: invalid instruction encoding
432 # CHECK-NEXT: [0xb3 0x09 0x03 0xf4]
433
434 # size == '11' ==> UNDEFINED
435 [0xc3 0x08 0x03 0xf4]
436 # CHECK: invalid instruction encoding
437 # CHECK-NEXT: [0xc3 0x08 0x03 0xf4]
438
439 # type == '1000' and align == '11' ==> UNDEFINED
440 [0xb3 0x08 0x03 0xf4]
441 # CHECK: invalid instruction encoding
442 # CHECK-NEXT: [0xb3 0x08 0x03 0xf4]
443
444 # VST1 multi-element, type == 0b0111, align == 0b10 -> undefined
445 [0xaf 0xb7 0x07 0xf4]
446 # CHECK: invalid instruction encoding
447 # CHECK-NEXT: [0xaf 0xb7 0x07 0xf4]
448
449 # VST1 multi-element, type == 0b0111, align == 0b11 -> undefined
450 [0xbf 0xb7 0x07 0xf4]
451 # CHECK: invalid instruction encoding
452 # CHECK-NEXT: [0xbf 0xb7 0x07 0xf4]
453
454 # VST1 multi-element, type == 0b1010, align == 0b11 -> undefined
455 [0xbf 0x8a 0x03 0xf4]
456 # CHECK: invalid instruction encoding
457 # CHECK-NEXT: [0xbf 0x8a 0x03 0xf4]
458
459 # VST1 multi-element, type == 0b0110, align == 0b10 -> undefined
460 [0xaf 0xb6 0x07 0xf4]
461 # CHECK: invalid instruction encoding
462 # CHECK-NEXT: [0xaf 0xb6 0x07 0xf4]
463
464 # VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
465 [0xbf 0xb6 0x07 0xf4]
466 # CHECK: invalid instruction encoding
467 # CHECK-NEXT: [0xbf 0xb6 0x07 0xf4]
468
469 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
470 [0x4f 0xa8 0x07 0xf7]
471 # CHECK: invalid instruction encoding
472 # CHECK-NEXT: [0x4f 0xa8 0x07 0xf7]
473
474 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
475 [0x4f 0xa9 0x07 0xf7]
476 # CHECK: invalid instruction encoding
477 # CHECK-NEXT: [0x4f 0xa9 0x07 0xf7]
478
479 # VST3 multi-element, size = 0b11 -> undefined
480 [0xbf 0xa4 0x0b 0xf4]
481 # CHECK: invalid instruction encoding
482 # CHECK-NEXT: [0xbf 0xa4 0x0b 0xf4]
483
484 # VST3 multi-element, align = 0b10 -> undefined
485 [0x6f 0xa4 0x0b 0xf4]
486 # CHECK: invalid instruction encoding
487 # CHECK-NEXT: [0x6f 0xa4 0x0b 0xf4]
488
489 # VST3 multi-element, align = 0b11 -> undefined
490 [0x7f 0xa4 0x0b 0xf4]
491 # CHECK: invalid instruction encoding
492 # CHECK-NEXT: [0x7f 0xa4 0x0b 0xf4]
493
494 # VST4 multi-element, size = 0b11 -> undefined
495 [0xcf 0x50 0x03 0xf4]
496 # CHECK: invalid instruction encoding
497 # CHECK-NEXT: [0xcf 0x50 0x03 0xf4]
498
499
500 # Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30)
501 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
502 # -------------------------------------------------------------------------------------------------
503 # | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1|
504 # -------------------------------------------------------------------------------------------------
505 #
506 # 'a' == 1 and data_size == 8 is invalid
507 [0x3d 0x3c 0xa0 0xf4]
508 # CHECK: invalid instruction encoding
509 # CHECK-NEXT: [0x3d 0x3c 0xa0 0xf4]
0 # RUN: llvm-mc -disassemble -triple armv7 -show-encoding < %s 2>&1 | FileCheck %s
1
2 # This file is checking encodings that are valid on some triples, but not on the
3 # ARMv7 triple, probably because the relevant instruction is v8, though there
4 # could be other reasons.
5
6 # Would be vcvtt.f64.f16 d3, s1
7 [0xe0 0x3b 0xb2 0xee]
8 # CHECK: invalid instruction encoding
9 # CHECK-NEXT: [0xe0 0x3b 0xb2 0xee]
10
11 # Would be vcvtb.f16.f64 s4, d1
12 [0x41 0x2b 0xb3 0xee]
13 # CHECK: invalid instruction encoding
14 # CHECK-NEXT: [0x41 0x2b 0xb3 0xee]
15
16 # Would be vcvtblt.f16.f64 s4, d1
17 [0x41 0x2b 0xb3 0xbe]
18 # CHECK: invalid instruction encoding
19 # CHECK-NEXT: [0x41 0x2b 0xb3 0xbe]
+0
-13
test/MC/Disassembler/ARM/invalid-hint-arm.txt less more
None # RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s 2>&1 | FileCheck %s
1
2 #------------------------------------------------------------------------------
3 # Undefined encoding space for hint instructions
4 #------------------------------------------------------------------------------
5
6 0x05 0xf0 0x20 0xe3
7 # CHECK: invalid instruction encoding
8 0x41 0xf0 0x20 0xe3
9 # CHECK: invalid instruction encoding
10 0xfe 0xf0 0x20 0xe3
11 # CHECK: invalid instruction encoding
12
+0
-8
test/MC/Disassembler/ARM/invalid-hint-thumb.txt less more
None # RUN: llvm-mc -triple=thumbv7 -disassemble -show-encoding < %s 2>&1 | FileCheck %s
1
2 #------------------------------------------------------------------------------
3 # Undefined encoding space for hint instructions
4 #------------------------------------------------------------------------------
5
6 0xaf 0xf3 0x05 0x80
7 # CHECK: invalid instruction encoding
+0
-11
test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # A8.6.16 B
9 # if cond<3:1> == '111' then SEE "Related Encodings"
10 0xaf 0xf7 0x44 0x8b
+0
-10
test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # The unpriviledged Load/Store cannot have SP or PC as Rt.
9 0x10 0xf8 0x3 0xfe
+0
-11
test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1 # XFAIL: *
2
3 # Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25)
4 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 # -------------------------------------------------------------------------------------------------
6 # | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 1| 0: 0: 1: 0| 1: 0: 0: 0| 1: 0: 0: 0| 0: 1: 1: 1| 1: 1: 1: 1|
7 # -------------------------------------------------------------------------------------------------
8 #
9 # if t == t2 then UNPREDICTABLE
10 0xd2 0xe8 0x7f 0x88
+0
-10
test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # if Rt = '1111' then SEE "Unallocated memory hints"
9 0xb3 0xf9 0xdf 0xf8
+0
-10
test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints"
9 0x35 0xf9 0x00 0xfc
+0
-5
test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # SP and PC are not allowed in the register list on STM instructions in Thumb2.
3
4 0x2d 0xe9 0xf7 0xb6
+0
-10
test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined"
1
2 # Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 0| 0: 1: 0: 0| 0: 1: 0: 0| 0: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 0|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # if wback && (n == t || n == t2) then UNPREDICTABLE
9 0xe4 0xe9 0x02 0x46
+0
-11
test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1 # XFAIL: *
2
3 # Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25)
4 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 # -------------------------------------------------------------------------------------------------
6 # | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 1: 0|
7 # -------------------------------------------------------------------------------------------------
8 #
9 # if d == n || d == t then UNPREDICTABLE
10 0xc2 0xe8 0x42 0x8f
+0
-10
test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # if d == n || d == t || d == t2 then UNPREDICTABLE
9 mc-input.txt:1:1: warning: invalid instruction encoding
+0
-10
test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt less more
None # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # if Rn == '1111' then UNDEFINED
9 0x4f 0xf8 0xff 0xeb
0 # RUN: llvm-mc -disassemble -triple thumbv7 2>&1 | FileCheck %s
1 # XFAIL: *
2
3 #------------------------------------------------------------------------------
4 # Undefined encodings for ldrexd/strexd
5 #------------------------------------------------------------------------------
6
7 # FIXME: "ldrexd r8, r8, [r2]"
8 # Rt == Rt2 is UNPREDICTABLE
9
10 [0xd2 0xe8 0x7f 0x88]
11 # CHECK: potentially undefined instruction encoding
12 # CHECK-NEXT: [0xd2 0xe8 0x7f 0x88]
13
14 # Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25)
15 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 # -------------------------------------------------------------------------------------------------
17 # | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 1: 0|
18 # -------------------------------------------------------------------------------------------------
19 #
20 # if d == n || d == t then UNPREDICTABLE
21
22 [0xc2 0xe8 0x42 0x8f]
23 # CHECK: potentially undefined instruction encoding
24 # CHECK-NEXT: [0xc2 0xe8 0x42 0x8f]
25
26 # Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25)
27 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
28 # -------------------------------------------------------------------------------------------------
29 # | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0|
30 # -------------------------------------------------------------------------------------------------
31 #
32 # if d == n || d == t || d == t2 then UNPREDICTABLE
33
34 # FIXME: should be unpredictable since it's "strexd r8, r7, r8, [r2]"
35 [0xc2 0xe8 0x78 0x78]
36 # CHECK: potentially undefined instruction encoding
37 # CHECK-NEXT: [0xc2 0xe8 0x78 0x78]
0 # RUN: llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s
1
2 # This file is checking Thumbv7 encodings which are globally invalid, usually due
3 # to the constraints of the instructions not being met. For example invalid
4 # combinations of registers.
5
6 #------------------------------------------------------------------------------
7 # Undefined encoding for b.cc
8 #------------------------------------------------------------------------------
9
10 # Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25)
11 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
12 # -------------------------------------------------------------------------------------------------
13 # | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0|
14 # -------------------------------------------------------------------------------------------------
15 #
16 # A8.6.16 B
17 # if cond<3:1> == '111' then SEE "Related Encodings"
18
19 [0xaf 0xf7 0x44 0x8b]
20 # CHECK: warning: invalid instruction encoding
21 # CHECK-NEXT: [0xaf 0xf7 0x44 0x8b]
22
23 # Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25)
24 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
25 # -------------------------------------------------------------------------------------------------
26 # | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1|
27 # -------------------------------------------------------------------------------------------------
28 #
29 # if cond = '1110' then UNDEFINED
30 [0x6f 0xde]
31 # CHECK: invalid instruction encoding
32 # CHECK-NEXT: [0x6f 0xde]
33
34
35 #------------------------------------------------------------------------------
36 # Undefined encoding space for hint instructions
37 #------------------------------------------------------------------------------
38
39 [0xaf 0xf3 0x05 0x80]
40 # CHECK: invalid instruction encoding
41 # CHECK-NEXT: [0xaf 0xf3 0x05 0x80]
42
43
44 #------------------------------------------------------------------------------
45 # Undefined encoding for it
46 #------------------------------------------------------------------------------
47
48 [0xff 0xbf 0x6b 0x80 0x00 0x75]
49 # CHECK: potentially undefined instruction encoding
50 # CHECK-NEXT: [0xff 0xbf 0x6b 0x80 0x00 0x75]
51
52 # mask = 0
53 [0x50 0xbf 0x00 0x00]
54 # CHECK: invalid instruction encoding
55 # CHECK-NEXT: [0x50 0xbf 0x00 0x00]
56
57 # Two warnings from this block since there are two instructions in there
58 [0xdb 0xbf 0x42 0xbb]
59 # CHECK: potentially undefined instruction encoding
60 # CHECK-NEXT: [0xdb 0xbf 0x42 0xbb]
61 # CHECK: potentially undefined instruction encoding
62 # CHECK-NEXT: [0xdb 0xbf 0x42 0xbb]
63
64 #------------------------------------------------------------------------------
65 # Undefined encoding for ldm
66 #------------------------------------------------------------------------------
67
68 # Writeback is not allowed is Rn is in the target register list.
69 [0xb4 0xe8 0x34 0x04]
70 # CHECK: potentially undefined instruction encoding
71 # CHECK-NEXT: [0xb4 0xe8 0x34 0x04]
72
73
74 #------------------------------------------------------------------------------
75 # Undefined encoding for ldrd
76 #------------------------------------------------------------------------------
77
78 # Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
79 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
80 # -------------------------------------------------------------------------------------------------
81 # | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
82 # -------------------------------------------------------------------------------------------------
83 #
84 # A8.6.66 LDRD (immediate)
85 # if Rn = '1111' then SEE LDRD (literal)
86 # A8.6.67 LDRD (literal)
87 # Inst{21} = 0
88
89 [0xff 0xe9 0x0 0xeb]
90 # CHECK: potentially undefined
91 # CHECK-NEXT: [0xff 0xe9 0x0 0xeb]
92
93
94 #------------------------------------------------------------------------------
95 # Undefined encodings for ldrbt
96 #------------------------------------------------------------------------------
97
98 # Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25)
99 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
100 # -------------------------------------------------------------------------------------------------
101 # | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1|
102 # -------------------------------------------------------------------------------------------------
103 #
104 # The unpriviledged Load/Store cannot have SP or PC as Rt.
105 [0x10 0xf8 0x3 0xfe]
106 # CHECK: potentially undefined instruction encoding
107 # CHECK-NEXT: [0x10 0xf8 0x3 0xfe]
108
109
110 #------------------------------------------------------------------------------
111 # Undefined encodings for ldrsh
112 #------------------------------------------------------------------------------
113
114 # invalid LDRSHs Rt=PC
115 [0x30 0xf9 0x00 0xf0]
116 # CHECK: invalid instruction encoding
117 # CHECK-NEXT: [0x30 0xf9 0x00 0xf0]
118
119 # invalid LDRSHi8 Rt=PC
120 [0x30 0xf9 0x00 0xfc]
121 # CHECK: invalid instruction encoding
122 # CHECK-NEXT: [0x30 0xf9 0x00 0xfc]
123
124 # invalid LDRSHi12 Rt=PC
125 [0xb0 0xf9 0x00 0xf0]
126 # CHECK: invalid instruction encoding
127 # CHECK-NEXT: [0xb0 0xf9 0x00 0xf0]
128
129 # Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25)
130 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
131 # -------------------------------------------------------------------------------------------------
132 # | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
133 # -------------------------------------------------------------------------------------------------
134 #
135 # if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints"
136 [0x35 0xf9 0x00 0xfc]
137 # CHECK: invalid instruction encoding
138 # CHECK-NEXT: [0x35 0xf9 0x00 0xfc]
139
140 # Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25)
141 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
142 # -------------------------------------------------------------------------------------------------
143 # | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1|
144 # -------------------------------------------------------------------------------------------------
145 #
146 # if Rt = '1111' then SEE "Unallocated memory hints"
147 [0xb3 0xf9 0xdf 0xf8]
148 # CHECK: invalid instruction encoding
149 # CHECK-NEXT: [0xb3 0xf9 0xdf 0xf8]
150
151
152 #------------------------------------------------------------------------------
153 # Undefined encoding for push
154 #------------------------------------------------------------------------------
155
156 # SP and PC are not allowed in the register list on STM instructions in Thumb2.
157 [0x2d 0xe9 0xf7 0xb6]
158 # CHECK: invalid instruction encoding
159 # CHECK-NEXT: [0x2d 0xe9 0xf7 0xb6]
160
161
162 #------------------------------------------------------------------------------
163 # Undefined encoding for stmia
164 #------------------------------------------------------------------------------
165
166 # Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25)
167 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
168 # -------------------------------------------------------------------------------------------------
169 # | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
170 # -------------------------------------------------------------------------------------------------
171 #
172 # if BitCount(registers) < 1 then UNPREDICTABLE
173 [0x00 0xc7]
174 # CHECK: invalid instruction encoding
175 # CHECK-NEXT: [0x00 0xc7]
176
177
178 #------------------------------------------------------------------------------
179 # Undefined encodings for str
180 #------------------------------------------------------------------------------
181
182 # invalid STRi12 Rn=PC
183 [0xcf 0xf8 0x00 0x00]
184 # CHECK: invalid instruction encoding
185 # CHECK-NEXT: [0xcf 0xf8 0x00 0x00]
186
187 # invalid STRi8 Rn=PC
188 [0x4f 0xf8 0x00 0x0c]
189 # CHECK: invalid instruction encoding
190 # CHECK-NEXT: [0x4f 0xf8 0x00 0x0c]
191
192 # invalid STRs Rn=PC
193 [0x4f 0xf8 0x00 0x00]
194 # CHECK: invalid instruction encoding
195 # CHECK-NEXT: [0x4f 0xf8 0x00 0x00]
196
197 # invalid STRBi12 Rn=PC
198 [0x0f 0xf8 0x00 0x00]
199 # CHECK: invalid instruction encoding
200 # CHECK-NEXT: [0x0f 0xf8 0x00 0x00]
201
202 # invalid STRBi8 Rn=PC
203 [0x0f 0xf8 0x00 0x0c]
204 # CHECK: invalid instruction encoding
205 # CHECK-NEXT: [0x0f 0xf8 0x00 0x0c]
206
207 # invalid STRBs Rn=PC
208 [0x0f 0xf8 0x00 0x00]
209 # CHECK: invalid instruction encoding
210 # CHECK-NEXT: [0x0f 0xf8 0x00 0x00]
211
212 # invalid STRHi12 Rn=PC
213 [0xaf 0xf8 0x00 0x00]
214 # CHECK: invalid instruction encoding
215 # CHECK-NEXT: [0xaf 0xf8 0x00 0x00]
216
217 # invalid STRHi8 Rn=PC
218 [0x2f 0xf8 0x00 0x0c]
219 # CHECK: invalid instruction encoding
220 # CHECK-NEXT: [0x2f 0xf8 0x00 0x0c]
221
222 # invalid STRHs Rn=PC
223 [0x2f 0xf8 0x00 0x00]
224 # CHECK: invalid instruction encoding
225 # CHECK-NEXT: [0x2f 0xf8 0x00 0x00]
226
227 # invalid STRBT Rn=PC
228 [0x0f 0xf8 0x00 0x0e]
229 # CHECK: invalid instruction encoding
230 # CHECK-NEXT: [0x0f 0xf8 0x00 0x0e]
231
232 # invalid STRHT Rn=PC
233 [0x2f 0xf8 0x00 0x0e]
234 # CHECK: invalid instruction encoding
235 # CHECK-NEXT: [0x2f 0xf8 0x00 0x0e]
236
237 # invalid STRT Rn=PC
238 [0x4f 0xf8 0x00 0x0e]
239 # CHECK: invalid instruction encoding
240 # CHECK-NEXT: [0x4f 0xf8 0x00 0x0e]
241
242 # Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25)
243 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
244 # -------------------------------------------------------------------------------------------------
245 # | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1|
246 # -------------------------------------------------------------------------------------------------
247 #
248 # if Rn == '1111' then UNDEFINED
249
250 [0x4f 0xf8 0xff 0xeb]
251 # CHECK: invalid instruction encoding
252 # CHECK-NEXT: [0x4f 0xf8 0xff 0xeb]
253
254 #------------------------------------------------------------------------------
255 # Undefined encodings for strd
256 #------------------------------------------------------------------------------
257
258 # Rt == Rn is UNPREDICTABLE
259 [0xe4 0xe9 0x02 0x46]
260 # CHECK: warning: potentially undefined instruction encoding
261 # CHECK-NEXT: [0xe4 0xe9 0x02 0x46]
262
263 #------------------------------------------------------------------------------
264 # Undefined encodings for NEON/VFP instructions with invalid predicate bits
265 #------------------------------------------------------------------------------
266
267 # VABS
268 [0x40 0xde 0x00 0x0a]
269 # CHECK: invalid instruction encoding
270 # CHECK-NEXT: [0x40 0xde 0x00 0x0a]
271
272
273 # VMLA
274 [0xf0 0xde 0xe0 0x0b]
275 # CHECK: invalid instruction encoding
276 # CHECK-NEXT: [0xf0 0xde 0xe0 0x0b]
277
278 # VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110)
279
280 # VMOV
281 [0x00 0xde 0x10 0x0b]
282 # CHECK: invalid instruction encoding
283 # CHECK-NEXT: [0x00 0xde 0x10 0x0b]
284
285 # VDUP
286 [0xff 0xde 0xf0 0xfb]
287 # CHECK: invalid instruction encoding
288 # CHECK-NEXT: [0xff 0xde 0xf0 0xfb]
289
290
291 #------------------------------------------------------------------------------
292 # Undefined encodings for NEON vld instructions
293 #------------------------------------------------------------------------------
294
295 # size = '00' and index_align == '0001' so UNDEFINED
296 [0xa0 0xf9 0x10 0x08]
297 # CHECK: invalid instruction encoding
298 # CHECK-NEXT: [0xa0 0xf9 0x10 0x08]
299
300
301 # vld3
302
303 # Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30)
304 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
305 # -------------------------------------------------------------------------------------------------
306 # | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0|
307 # -------------------------------------------------------------------------------------------------
308 #
309 # A8.6.315 VLD3 (single 3-element structure to all lanes)
310 # The a bit must be encoded as 0.
311
312 [0xa2 0xf9 0x92 0x2e]
313 # CHECK: invalid instruction encoding
314 # CHECK-NEXT: [0xa2 0xf9 0x92 0x2e]
315
316
317 # Some vld4 ones
318 # size == '11' and a == '0' so UNDEFINED
319 [0xa0 0xf9 0xc0 0x0f]
320 # CHECK: invalid instruction encoding
321 # CHECK-NEXT: [0xa0 0xf9 0xc0 0x0f]
322
323 [0xa0 0xf9 0x30 0x0b]
324 # CHECK: invalid instruction encoding
325 # CHECK-NEXT: [0xa0 0xf9 0x30 0x0b]
326
327
328 # VLD1 multi-element, type=0b1010 align=0b11
329 [0x24 0xf9 0xbf 0x8a]
330 # CHECK: invalid instruction encoding
331 # CHECK-NEXT: [0x24 0xf9 0xbf 0x8a]
332
333 # VLD1 multi-element type=0b0111 align=0b1x
334 [0x24 0xf9 0xbf 0x87]
335 # CHECK: invalid instruction encoding
336 # CHECK-NEXT: [0x24 0xf9 0xbf 0x87]
337
338 # VLD1 multi-element type=0b0010 align=0b1x
339 [0x24 0xf9 0xbf 0x86]
340 # CHECK: invalid instruction encoding
341 # CHECK-NEXT: [0x24 0xf9 0xbf 0x86]
342
343 # VLD2 multi-element size=0b11
344 [0x60 0xf9 0xcf 0x08]
345 # CHECK: invalid instruction encoding
346 # CHECK-NEXT: [0x60 0xf9 0xcf 0x08]
347
348 # VLD2 multi-element type=0b1111 align=0b11
349 [0x60 0xf9 0xbf 0x08]
350 # CHECK: invalid instruction encoding
351 # CHECK-NEXT: [0x60 0xf9 0xbf 0x08]
352
353 # VLD2 multi-element type=0b1001 align=0b11
354 [0x60 0xf9 0xbf 0x09]
355 # CHECK: invalid instruction encoding
356 # CHECK-NEXT: [0x60 0xf9 0xbf 0x09]
357
358 # VLD3 multi-element size=0b11
359 [0x60 0xf9 0x7f 0x04]
360 # CHECK: invalid instruction encoding
361 # CHECK-NEXT: [0x60 0xf9 0x7f 0x04]
362
363 # VLD3 multi-element align=0b1x
364 [0x60 0xf9 0xcf 0x04]
365 # CHECK: invalid instruction encoding
366 # CHECK-NEXT: [0x60 0xf9 0xcf 0x04]
367
368 # VLD4 multi-element size=0b11
369 [0x60 0xf9 0xcd 0x11]
370 # CHECK: invalid instruction encoding
371 # CHECK-NEXT: [0x60 0xf9 0xcd 0x11]
372
373
374 #------------------------------------------------------------------------------
375 # Undefined encodings for NEON vst1
376 #------------------------------------------------------------------------------
377
378 # size == '10' and index_align == '0001' so UNDEFINED
379 [0x80 0xf9 0x10 0x08]
380 # CHECK: invalid instruction encoding
381 # CHECK-NEXT: [0x80 0xf9 0x10 0x08]
382
383 # Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30)
384 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
385 # -------------------------------------------------------------------------------------------------
386 # | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1|
387 # -------------------------------------------------------------------------------------------------
388 #
389 # A8.6.391 VST1 (multiple single elements)
390 # This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128]
391 # But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if
392 # contains two or four registers. rdar://11220250
393 [0x00 0xf9 0x2f 0x06]
394 # CHECK: invalid instruction encoding
395 # CHECK-NEXT: [0x00 0xf9 0x2f 0x06]
396
397 #------------------------------------------------------------------------------
398 # Undefined encodings for NEON vst4
399 #------------------------------------------------------------------------------
400
401 [0x80 0xf9 0x30 0x0b]
402 # CHECK: invalid instruction encoding
403 # CHECK-NEXT: [0x80 0xf9 0x30 0x0b]
+0
-10
test/MC/Disassembler/ARM/invalid-v8fp.txt less more
None # RUN: llvm-mc -disassemble -triple armv7 -show-encoding < %s | FileCheck %s
1
2 0xe0 0x3b 0xb2 0xee
3 # CHECK-NOT: vcvtt.f64.f16 d3, s1
4
5 0x41 0x2b 0xb3 0xee
6 # CHECK-NOT: vcvtb.f16.f64 s4, d1
7
8 0x41 0x2b 0xb3 0xbe
9 # CHECK-NOT: vcvtblt.f16.f64 s4, d1
5050 static bool PrintInsts(const MCDisassembler &DisAsm,
5151 const ByteArrayTy &Bytes,
5252 SourceMgr &SM, raw_ostream &Out,
53 MCStreamer &Streamer) {
53 MCStreamer &Streamer, bool InAtomicBlock) {
5454 // Wrap the vector in a MemoryObject.
5555 VectorMemoryObject memoryObject(Bytes);
5656
6969 SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second),
7070 SourceMgr::DK_Warning,
7171 "invalid instruction encoding");
72 // Don't try to resynchronise the stream in a block
73 if (InAtomicBlock)
74 return true;
75
7276 if (Size == 0)
7377 Size = 1; // skip illegible bytes
78
7479 break;
7580
7681 case MCDisassembler::SoftFail:
8893 return false;
8994 }
9095
91 static bool ByteArrayFromString(ByteArrayTy &ByteArray,
92 StringRef &Str,
93 SourceMgr &SM) {
94 while (!Str.empty()) {
95 // Strip horizontal whitespace.
96 if (size_t Pos = Str.find_first_not_of(" \t\r")) {
96 static bool SkipToToken(StringRef &Str) {
97 while (!Str.empty() && Str.find_first_not_of(" \t\r\n#,") != 0) {
98 // Strip horizontal whitespace and commas.
99 if (size_t Pos = Str.find_first_not_of(" \t\r,")) {
97100 Str = Str.substr(Pos);
98 continue;
99101 }
100102
101103 // If this is the end of a line or start of a comment, remove the rest of
112114 }
113115 continue;
114116 }
117 }
118
119 return !Str.empty();
120 }
121
122
123 static bool ByteArrayFromString(ByteArrayTy &ByteArray,
124 StringRef &Str,
125 SourceMgr &SM) {
126 while (SkipToToken(Str)) {
127 // Handled by higher level
128 if (Str[0] == '[' || Str[0] == ']')
129 return false;
115130
116131 // Get the current token.
117 size_t Next = Str.find_first_of(" \t\n\r#");
132 size_t Next = Str.find_first_of(" \t\n\r,#[]");
118133 StringRef Value = Str.substr(0, Next);
119134
120135 // Convert to a byte and add to the byte vector.
156171 // Convert the input to a vector for disassembly.
157172 ByteArrayTy ByteArray;
158173 StringRef Str = Buffer.getBuffer();
159
160 ErrorOccurred |= ByteArrayFromString(ByteArray, Str, SM);
161
162 if (!ByteArray.empty())
163 ErrorOccurred |= PrintInsts(*DisAsm, ByteArray, SM, Out, Streamer);
174 bool InAtomicBlock = false;
175
176 while (SkipToToken(Str)) {
177 ByteArray.clear();
178
179 if (Str[0] == '[') {
180 if (InAtomicBlock) {
181 SM.PrintMessage(SMLoc::getFromPointer(Str.data()), SourceMgr::DK_Error,
182 "nested atomic blocks make no sense");
183 ErrorOccurred = true;
184 }
185 InAtomicBlock = true;
186 Str = Str.drop_front();
187 continue;
188 } else if (Str[0] == ']') {
189 if (!InAtomicBlock) {
190 SM.PrintMessage(SMLoc::getFromPointer(Str.data()), SourceMgr::DK_Error,
191 "attempt to close atomic block without opening");
192 ErrorOccurred = true;
193 }
194 InAtomicBlock = false;
195 Str = Str.drop_front();
196 continue;
197 }
198
199 // It's a real token, get the bytes and emit them
200 ErrorOccurred |= ByteArrayFromString(ByteArray, Str, SM);
201
202 if (!ByteArray.empty())
203 ErrorOccurred |= PrintInsts(*DisAsm, ByteArray, SM, Out, Streamer,
204 InAtomicBlock);
205 }
206
207 if (InAtomicBlock) {
208 SM.PrintMessage(SMLoc::getFromPointer(Str.data()), SourceMgr::DK_Error,
209 "unclosed atomic block");
210 ErrorOccurred = true;
211 }
164212
165213 return ErrorOccurred;
166214 }