llvm.org GIT mirror llvm / 385e930
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 9 years ago
54 changed file(s) with 57 addition(s) and 60 deletion(s). Raw diff Collapse all Expand all
17741774 $(Echo) "Building $(
17751775 $(Verb) $(TableGen) -gen-fast-isel -o $(call SYSPATH, $@) $<
17761776
1777 $(TARGET:%=$(ObjDir)/%GenSubtarget.inc.tmp): \
1778 $(ObjDir)/%GenSubtarget.inc.tmp : %.td $(ObjDir)/.dir
1777 $(TARGET:%=$(ObjDir)/%GenSubtargetInfo.inc.tmp): \
1778 $(ObjDir)/%GenSubtargetInfo.inc.tmp : %.td $(ObjDir)/.dir
17791779 $(Echo) "Building $(
17801780 $(Verb) $(TableGen) -gen-subtarget -o $(call SYSPATH, $@) $<
17811781
2020 #define GET_SUBTARGETINFO_CTOR
2121 #define GET_SUBTARGETINFO_MC_DESC
2222 #define GET_SUBTARGETINFO_TARGET_DESC
23 #include "ARMGenSubtarget.inc"
23 #include "ARMGenSubtargetInfo.inc"
2424
2525 using namespace llvm;
2626
1919 #include
2020
2121 #define GET_SUBTARGETINFO_HEADER
22 #include "ARMGenSubtarget.inc"
22 #include "ARMGenSubtargetInfo.inc"
2323
2424 namespace llvm {
2525 class GlobalValue;
88 tablegen(ARMGenDAGISel.inc -gen-dag-isel)
99 tablegen(ARMGenFastISel.inc -gen-fast-isel)
1010 tablegen(ARMGenCallingConv.inc -gen-callingconv)
11 tablegen(ARMGenSubtarget.inc -gen-subtarget)
11 tablegen(ARMGenSubtargetInfo.inc -gen-subtarget)
1212 tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
1313 tablegen(ARMGenDecoderTables.inc -gen-arm-decoder)
1414
1313 # Make sure that tblgen is run, first thing.
1414 BUILT_SOURCES = ARMGenRegisterInfo.inc ARMGenInstrInfo.inc \
1515 ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
16 ARMGenDAGISel.inc ARMGenSubtarget.inc \
16 ARMGenDAGISel.inc ARMGenSubtargetInfo.inc \
1717 ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
1818 ARMGenDecoderTables.inc ARMGenEDInfo.inc \
1919 ARMGenFastISel.inc ARMGenMCCodeEmitter.inc
1212
1313 #include "AlphaSubtarget.h"
1414 #include "Alpha.h"
15 #include "AlphaGenSubtarget.inc"
1615
1716 #define GET_SUBTARGETINFO_CTOR
1817 #define GET_SUBTARGETINFO_MC_DESC
1918 #define GET_SUBTARGETINFO_TARGET_DESC
20 #include "AlphaGenSubtarget.inc"
19 #include "AlphaGenSubtargetInfo.inc"
2120
2221 using namespace llvm;
2322
1818 #include
1919
2020 #define GET_SUBTARGETINFO_HEADER
21 #include "AlphaGenSubtarget.inc"
21 #include "AlphaGenSubtargetInfo.inc"
2222
2323 namespace llvm {
2424
44 tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
55 tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
66 tablegen(AlphaGenCallingConv.inc -gen-callingconv)
7 tablegen(AlphaGenSubtarget.inc -gen-subtarget)
7 tablegen(AlphaGenSubtargetInfo.inc -gen-subtarget)
88
99 add_llvm_target(AlphaCodeGen
1010 AlphaAsmPrinter.cpp
1313 # Make sure that tblgen is run, first thing.
1414 BUILT_SOURCES = AlphaGenRegisterInfo.inc AlphaGenInstrInfo.inc \
1515 AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
16 AlphaGenCallingConv.inc AlphaGenSubtarget.inc
16 AlphaGenCallingConv.inc AlphaGenSubtargetInfo.inc
1717
1818 DIRS = TargetInfo
1919
1515 #define GET_SUBTARGETINFO_CTOR
1616 #define GET_SUBTARGETINFO_MC_DESC
1717 #define GET_SUBTARGETINFO_TARGET_DESC
18 #include "BlackfinGenSubtarget.inc"
18 #include "BlackfinGenSubtargetInfo.inc"
1919
2020 using namespace llvm;
2121
1717 #include
1818
1919 #define GET_SUBTARGETINFO_HEADER
20 #include "BlackfinGenSubtarget.inc"
20 #include "BlackfinGenSubtargetInfo.inc"
2121
2222 namespace llvm {
2323
33 tablegen(BlackfinGenInstrInfo.inc -gen-instr-info)
44 tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)
55 tablegen(BlackfinGenDAGISel.inc -gen-dag-isel)
6 tablegen(BlackfinGenSubtarget.inc -gen-subtarget)
6 tablegen(BlackfinGenSubtargetInfo.inc -gen-subtarget)
77 tablegen(BlackfinGenCallingConv.inc -gen-callingconv)
88 tablegen(BlackfinGenIntrinsics.inc -gen-tgt-intrinsic)
99
1313 # Make sure that tblgen is run, first thing.
1414 BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrInfo.inc \
1515 BlackfinGenAsmWriter.inc \
16 BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
16 BlackfinGenDAGISel.inc BlackfinGenSubtargetInfo.inc \
1717 BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
1818
1919 DIRS = TargetInfo
44 tablegen(SPUGenRegisterInfo.inc -gen-register-info)
55 tablegen(SPUGenInstrInfo.inc -gen-instr-info)
66 tablegen(SPUGenDAGISel.inc -gen-dag-isel)
7 tablegen(SPUGenSubtarget.inc -gen-subtarget)
7 tablegen(SPUGenSubtargetInfo.inc -gen-subtarget)
88 tablegen(SPUGenCallingConv.inc -gen-callingconv)
99
1010 add_llvm_target(CellSPUCodeGen
1212 BUILT_SOURCES = SPUGenInstrInfo.inc SPUGenRegisterInfo.inc \
1313 SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
1414 SPUGenDAGISel.inc \
15 SPUGenSubtarget.inc SPUGenCallingConv.inc
15 SPUGenSubtargetInfo.inc SPUGenCallingConv.inc
1616
1717 DIRS = TargetInfo
1818
1818 #define GET_SUBTARGETINFO_CTOR
1919 #define GET_SUBTARGETINFO_MC_DESC
2020 #define GET_SUBTARGETINFO_TARGET_DESC
21 #include "SPUGenSubtarget.inc"
21 #include "SPUGenSubtargetInfo.inc"
2222
2323 using namespace llvm;
2424
1818 #include
1919
2020 #define GET_SUBTARGETINFO_HEADER
21 #include "SPUGenSubtarget.inc"
21 #include "SPUGenSubtargetInfo.inc"
2222
2323 namespace llvm {
2424 class GlobalValue;
66 tablegen(MBlazeGenAsmMatcher.inc -gen-asm-matcher)
77 tablegen(MBlazeGenDAGISel.inc -gen-dag-isel)
88 tablegen(MBlazeGenCallingConv.inc -gen-callingconv)
9 tablegen(MBlazeGenSubtarget.inc -gen-subtarget)
9 tablegen(MBlazeGenSubtargetInfo.inc -gen-subtarget)
1010 tablegen(MBlazeGenIntrinsics.inc -gen-tgt-intrinsic)
1111 tablegen(MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info)
1212
1818 #define GET_SUBTARGETINFO_CTOR
1919 #define GET_SUBTARGETINFO_MC_DESC
2020 #define GET_SUBTARGETINFO_TARGET_DESC
21 #include "MBlazeGenSubtarget.inc"
21 #include "MBlazeGenSubtargetInfo.inc"
2222
2323 using namespace llvm;
2424
1818 #include
1919
2020 #define GET_SUBTARGETINFO_HEADER
21 #include "MBlazeGenSubtarget.inc"
21 #include "MBlazeGenSubtargetInfo.inc"
2222
2323 namespace llvm {
2424
1414 MBlazeGenAsmWriter.inc \
1515 MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
1616 MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
17 MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
17 MBlazeGenSubtargetInfo.inc MBlazeGenIntrinsics.inc \
1818 MBlazeGenEDInfo.inc
1919
2020 DIRS = InstPrinter AsmParser Disassembler TargetInfo
44 tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
55 tablegen(MSP430GenDAGISel.inc -gen-dag-isel)
66 tablegen(MSP430GenCallingConv.inc -gen-callingconv)
7 tablegen(MSP430GenSubtarget.inc -gen-subtarget)
7 tablegen(MSP430GenSubtargetInfo.inc -gen-subtarget)
88
99 add_llvm_target(MSP430CodeGen
1010 MSP430BranchSelector.cpp
1616 #define GET_SUBTARGETINFO_CTOR
1717 #define GET_SUBTARGETINFO_MC_DESC
1818 #define GET_SUBTARGETINFO_TARGET_DESC
19 #include "MSP430GenSubtarget.inc"
19 #include "MSP430GenSubtargetInfo.inc"
2020
2121 using namespace llvm;
2222
1616 #include "llvm/Target/TargetSubtargetInfo.h"
1717
1818 #define GET_SUBTARGETINFO_HEADER
19 #include "MSP430GenSubtarget.inc"
19 #include "MSP430GenSubtargetInfo.inc"
2020
2121 #include
2222
1414 BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrInfo.inc \
1515 MSP430GenAsmWriter.inc \
1616 MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
17 MSP430GenSubtarget.inc
17 MSP430GenSubtargetInfo.inc
1818
1919 DIRS = InstPrinter TargetInfo
2020
44 tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
55 tablegen(MipsGenDAGISel.inc -gen-dag-isel)
66 tablegen(MipsGenCallingConv.inc -gen-callingconv)
7 tablegen(MipsGenSubtarget.inc -gen-subtarget)
7 tablegen(MipsGenSubtargetInfo.inc -gen-subtarget)
88
99 add_llvm_target(MipsCodeGen
1010 MipsAsmPrinter.cpp
1414 BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
1515 MipsGenAsmWriter.inc \
1616 MipsGenDAGISel.inc MipsGenCallingConv.inc \
17 MipsGenSubtarget.inc
17 MipsGenSubtargetInfo.inc
1818
1919 DIRS = TargetInfo
2020
1616 #define GET_SUBTARGETINFO_CTOR
1717 #define GET_SUBTARGETINFO_MC_DESC
1818 #define GET_SUBTARGETINFO_TARGET_DESC
19 #include "MipsGenSubtarget.inc"
19 #include "MipsGenSubtargetInfo.inc"
2020
2121 using namespace llvm;
2222
1818 #include
1919
2020 #define GET_SUBTARGETINFO_HEADER
21 #include "MipsGenSubtarget.inc"
21 #include "MipsGenSubtargetInfo.inc"
2222
2323 namespace llvm {
2424
44 tablegen(PTXGenDAGISel.inc -gen-dag-isel)
55 tablegen(PTXGenInstrInfo.inc -gen-instr-info)
66 tablegen(PTXGenRegisterInfo.inc -gen-register-info)
7 tablegen(PTXGenSubtarget.inc -gen-subtarget)
7 tablegen(PTXGenSubtargetInfo.inc -gen-subtarget)
88
99 add_llvm_target(PTXCodeGen
1010 PTXAsmPrinter.cpp
1616 PTXGenDAGISel.inc \
1717 PTXGenInstrInfo.inc \
1818 PTXGenRegisterInfo.inc \
19 PTXGenSubtarget.inc
19 PTXGenSubtargetInfo.inc
2020
2121 DIRS = TargetInfo
2222
1616 #define GET_SUBTARGETINFO_CTOR
1717 #define GET_SUBTARGETINFO_MC_DESC
1818 #define GET_SUBTARGETINFO_TARGET_DESC
19 #include "PTXGenSubtarget.inc"
19 #include "PTXGenSubtargetInfo.inc"
2020
2121 using namespace llvm;
2222
6262 case PTX_VERSION_2_3: return "2.3";
6363 }
6464 }
65
66 #include "PTXGenSubtarget.inc"
1616 #include "llvm/Target/TargetSubtargetInfo.h"
1717
1818 #define GET_SUBTARGETINFO_HEADER
19 #include "PTXGenSubtarget.inc"
19 #include "PTXGenSubtargetInfo.inc"
2020
2121 namespace llvm {
2222 class PTXSubtarget : public PTXGenSubtargetInfo {
66 tablegen(PPCGenInstrInfo.inc -gen-instr-info)
77 tablegen(PPCGenDAGISel.inc -gen-dag-isel)
88 tablegen(PPCGenCallingConv.inc -gen-callingconv)
9 tablegen(PPCGenSubtarget.inc -gen-subtarget)
9 tablegen(PPCGenSubtargetInfo.inc -gen-subtarget)
1010
1111 add_llvm_target(PowerPCCodeGen
1212 PPCAsmBackend.cpp
1414 BUILT_SOURCES = PPCGenRegisterInfo.inc \
1515 PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
1616 PPCGenInstrInfo.inc PPCGenDAGISel.inc \
17 PPCGenSubtarget.inc PPCGenCallingConv.inc \
17 PPCGenSubtargetInfo.inc PPCGenCallingConv.inc \
1818 PPCGenMCCodeEmitter.inc
1919
2020 DIRS = InstPrinter TargetInfo
1919 #define GET_SUBTARGETINFO_CTOR
2020 #define GET_SUBTARGETINFO_MC_DESC
2121 #define GET_SUBTARGETINFO_TARGET_DESC
22 #include "PPCGenSubtarget.inc"
22 #include "PPCGenSubtargetInfo.inc"
2323
2424 using namespace llvm;
2525
1919 #include
2020
2121 #define GET_SUBTARGETINFO_HEADER
22 #include "PPCGenSubtarget.inc"
22 #include "PPCGenSubtargetInfo.inc"
2323
2424 // GCC #defines PPC on Linux but we use it as our namespace name
2525 #undef PPC
33 tablegen(SparcGenInstrInfo.inc -gen-instr-info)
44 tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
55 tablegen(SparcGenDAGISel.inc -gen-dag-isel)
6 tablegen(SparcGenSubtarget.inc -gen-subtarget)
6 tablegen(SparcGenSubtargetInfo.inc -gen-subtarget)
77 tablegen(SparcGenCallingConv.inc -gen-callingconv)
88
99 add_llvm_target(SparcCodeGen
1212
1313 # Make sure that tblgen is run, first thing.
1414 BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
15 SparcGenAsmWriter.inc \
16 SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc
15 SparcGenAsmWriter.inc SparcGenDAGISel.inc \
16 SparcGenSubtargetInfo.inc SparcGenCallingConv.inc
1717
1818 DIRS = TargetInfo
1919
1515 #define GET_SUBTARGETINFO_CTOR
1616 #define GET_SUBTARGETINFO_MC_DESC
1717 #define GET_SUBTARGETINFO_TARGET_DESC
18 #include "SparcGenSubtarget.inc"
18 #include "SparcGenSubtargetInfo.inc"
1919
2020 using namespace llvm;
2121
1717 #include
1818
1919 #define GET_SUBTARGETINFO_HEADER
20 #include "SparcGenSubtarget.inc"
20 #include "SparcGenSubtargetInfo.inc"
2121
2222 namespace llvm {
2323
44 tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)
55 tablegen(SystemZGenDAGISel.inc -gen-dag-isel)
66 tablegen(SystemZGenCallingConv.inc -gen-callingconv)
7 tablegen(SystemZGenSubtarget.inc -gen-subtarget)
7 tablegen(SystemZGenSubtargetInfo.inc -gen-subtarget)
88
99 add_llvm_target(SystemZCodeGen
1010 SystemZAsmPrinter.cpp
1212
1313 # Make sure that tblgen is run, first thing.
1414 BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrInfo.inc \
15 SystemZGenAsmWriter.inc \
16 SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc
15 SystemZGenAsmWriter.inc SystemZGenDAGISel.inc \
16 SystemZGenSubtargetInfo.inc SystemZGenCallingConv.inc
1717
1818 DIRS = TargetInfo
1919
1818 #define GET_SUBTARGETINFO_CTOR
1919 #define GET_SUBTARGETINFO_MC_DESC
2020 #define GET_SUBTARGETINFO_TARGET_DESC
21 #include "SystemZGenSubtarget.inc"
21 #include "SystemZGenSubtargetInfo.inc"
2222
2323 using namespace llvm;
2424
1717 #include
1818
1919 #define GET_SUBTARGETINFO_HEADER
20 #include "SystemZGenSubtarget.inc"
20 #include "SystemZGenSubtargetInfo.inc"
2121
2222 namespace llvm {
2323 class GlobalValue;
88 tablegen(X86GenDAGISel.inc -gen-dag-isel)
99 tablegen(X86GenFastISel.inc -gen-fast-isel)
1010 tablegen(X86GenCallingConv.inc -gen-callingconv)
11 tablegen(X86GenSubtarget.inc -gen-subtarget)
11 tablegen(X86GenSubtargetInfo.inc -gen-subtarget)
1212 tablegen(X86GenEDInfo.inc -gen-enhanced-disassembly-info)
1313
1414 set(sources
2323 #include "X86GenInstrInfo.inc"
2424
2525 #define GET_SUBTARGETINFO_MC_DESC
26 #include "X86GenSubtarget.inc"
26 #include "X86GenSubtargetInfo.inc"
2727
2828 using namespace llvm;
2929
1515 X86GenAsmWriter.inc X86GenAsmMatcher.inc \
1616 X86GenAsmWriter1.inc X86GenDAGISel.inc \
1717 X86GenDisassemblerTables.inc X86GenFastISel.inc \
18 X86GenCallingConv.inc X86GenSubtarget.inc \
18 X86GenCallingConv.inc X86GenSubtargetInfo.inc \
1919 X86GenEDInfo.inc
2020
2121 DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc Utils
2323 #define GET_SUBTARGETINFO_CTOR
2424 #define GET_SUBTARGETINFO_MC_DESC
2525 #define GET_SUBTARGETINFO_TARGET_DESC
26 #include "X86GenSubtarget.inc"
26 #include "X86GenSubtargetInfo.inc"
2727
2828 using namespace llvm;
2929
1919 #include
2020
2121 #define GET_SUBTARGETINFO_HEADER
22 #include "X86GenSubtarget.inc"
22 #include "X86GenSubtargetInfo.inc"
2323
2424 namespace llvm {
2525 class GlobalValue;
44 tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)
55 tablegen(XCoreGenDAGISel.inc -gen-dag-isel)
66 tablegen(XCoreGenCallingConv.inc -gen-callingconv)
7 tablegen(XCoreGenSubtarget.inc -gen-subtarget)
7 tablegen(XCoreGenSubtargetInfo.inc -gen-subtarget)
88
99 add_llvm_target(XCoreCodeGen
1010 XCoreAsmPrinter.cpp
1414 BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrInfo.inc \
1515 XCoreGenAsmWriter.inc \
1616 XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
17 XCoreGenSubtarget.inc
17 XCoreGenSubtargetInfo.inc
1818
1919 DIRS = TargetInfo
2020
1616 #define GET_SUBTARGETINFO_CTOR
1717 #define GET_SUBTARGETINFO_MC_DESC
1818 #define GET_SUBTARGETINFO_TARGET_DESC
19 #include "XCoreGenSubtarget.inc"
19 #include "XCoreGenSubtargetInfo.inc"
2020
2121 using namespace llvm;
2222
1818 #include
1919
2020 #define GET_SUBTARGETINFO_HEADER
21 #include "XCoreGenSubtarget.inc"
21 #include "XCoreGenSubtargetInfo.inc"
2222
2323 namespace llvm {
2424