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Merging r205067: ------------------------------------------------------------------------ r205067 | ahatanaka | 2014-03-28 19:28:07 -0400 (Fri, 28 Mar 2014) | 7 lines [x86] Fix printing of register operands with q modifier. Emit 32-bit register names instead of 64-bit register names if the target does not have 64-bit general purpose registers. <rdar://problem/14653996> ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206055 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 6 years ago
2 changed file(s) with 17 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
392392 case 'k': // Print SImode register
393393 Reg = getX86SubSuperRegister(Reg, MVT::i32);
394394 break;
395 case 'q': // Print DImode register
396 // FIXME: gcc will actually print e instead of r for 32-bit.
397 Reg = getX86SubSuperRegister(Reg, MVT::i64);
395 case 'q':
396 // Print 64-bit register names if 64-bit integer registers are available.
397 // Otherwise, print 32-bit register names.
398 MVT::SimpleValueType Ty = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
399 Reg = getX86SubSuperRegister(Reg, Ty);
398400 break;
399401 }
400402
0 ; RUN: llc < %s -march=x86 | FileCheck %s
1
2 ; If the target does not have 64-bit integer registers, emit 32-bit register
3 ; names.
4
5 ; CHECK: movq (%e{{[abcd]}}x, %ebx, 4)
6
7 define void @q_modifier(i32* %p) {
8 entry:
9 tail call void asm sideeffect "movq (${0:q}, %ebx, 4), %mm0", "r,~{dirflag},~{fpsr},~{flags}"(i32* %p)
10 ret void
11 }