llvm.org GIT mirror llvm / 37fefc2
Follow up to r138791. Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 9 years ago
12 changed file(s) with 64 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
115115 Commutable,
116116 ConvertibleTo3Addr,
117117 UsesCustomInserter,
118 HasPostISelHook,
118119 Rematerializable,
119120 CheapAsAMove,
120121 ExtraSrcRegAllocReq,
475476 return Flags & (1 << MCID::UsesCustomInserter);
476477 }
477478
479 /// hasPostISelHook - Return true if this instruction requires *adjustment*
480 /// after instruction selection by calling a target hook. For example, this
481 /// can be used to fill in ARM 's' optional operand depending on whether
482 /// the conditional flag register is used.
483 bool hasPostISelHook() const {
484 return Flags & (1 << MCID::HasPostISelHook);
485 }
486
478487 /// isRematerializable - Returns true if this instruction is a candidate for
479488 /// remat. This flag is deprecated, please don't use it anymore. If this
480489 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
327327 bit isPredicable = 0; // Is this instruction predicable?
328328 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
329329 bit usesCustomInserter = 0; // Pseudo instr needing special help.
330 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
330331 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
331332 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
332333 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
14701470 virtual MachineBasicBlock *
14711471 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
14721472
1473 /// AdjustInstrPostInstrSelection - This method should be implemented by
1474 /// targets that mark instructions with the 'hasPostISelHook' flag. These
1475 /// instructions must be adjusted after instruction selection by target hooks.
1476 /// e.g. To fill in optional defs for ARM 's' setting instructions.
1477 virtual void
1478 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
1479
14731480 //===--------------------------------------------------------------------===//
14741481 // Addressing mode description hooks (used by LSR etc).
14751482 //
760760 i != e; ++i)
761761 MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI);
762762 }
763
764 // Run post-isel target hook to adjust this instruction if needed.
765 if (II.hasPostISelHook())
766 TLI->AdjustInstrPostInstrSelection(MI, Node);
763767 }
764768
765769 /// EmitSpecialNode - Generate machine code for a target-independent node and
174174 #endif
175175 llvm_unreachable(0);
176176 return 0;
177 }
178
179 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
180 SDNode *Node) const {
181 #ifndef NDEBUG
182 dbgs() << "If a target marks an instruction with "
183 "'hasPostISelHook', it must implement "
184 "TargetLowering::AdjustInstrPostInstrSelection!";
185 #endif
186 llvm_unreachable(0);
177187 }
178188
179189 //===----------------------------------------------------------------------===//
54735473 }
54745474 }
54755475
5476 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
5477 SDNode *Node) const {
5478 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC,
5479 // RSB, RSC. Coming out of isel, they have an implicit CPSR def, but the
5480 // optional operand is not filled in. If the carry bit is used, then change
5481 // the optional operand to CPSR. Otherwise, remove the CPSR implicit def.
5482 const MCInstrDesc &MCID = MI->getDesc();
5483 if (Node->hasAnyUseOfValue(1)) {
5484 MachineOperand &MO = MI->getOperand(MCID.getNumOperands() - 2);
5485 MO.setReg(ARM::CPSR);
5486 MO.setIsDef(true);
5487 } else {
5488 for (unsigned i = MCID.getNumOperands(), e = MI->getNumOperands();
5489 i != e; ++i) {
5490 const MachineOperand &MO = MI->getOperand(i);
5491 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
5492 MI->RemoveOperand(i);
5493 break;
5494 }
5495 }
5496 }
5497 }
5498
54765499 //===----------------------------------------------------------------------===//
54775500 // ARM Optimization Hooks
54785501 //===----------------------------------------------------------------------===//
247247 virtual MachineBasicBlock *
248248 EmitInstrWithCustomInserter(MachineInstr *MI,
249249 MachineBasicBlock *MBB) const;
250
251 virtual void
252 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
250253
251254 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
252255 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
12891289 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
12901290 multiclass AI1_adde_sube_irs opcod, string opc, PatFrag opnode,
12911291 string baseOpc, bit Commutable = 0> {
1292 let Defs = [CPSR], Uses = [CPSR] in {
1292 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
12931293 def ri : AsI1
12941294 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
12951295 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
13771377 /// AI1_rsc_irs - Define instructions and patterns for rsc
13781378 multiclass AI1_rsc_irs opcod, string opc, PatFrag opnode,
13791379 string baseOpc> {
1380 let Defs = [CPSR], Uses = [CPSR] in {
1380 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
13811381 def ri : AsI1
13821382 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
13831383 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
16601660 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
16611661 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
16621662
1663 let hasPostISelHook = 1 in {
16631664 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
16641665 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
16651666 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
16661667 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1668 }
16671669
16681670 // RSB
16691671 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
308308 isReMaterializable = R->getValueAsBit("isReMaterializable");
309309 hasDelaySlot = R->getValueAsBit("hasDelaySlot");
310310 usesCustomInserter = R->getValueAsBit("usesCustomInserter");
311 hasPostISelHook = R->getValueAsBit("hasPostISelHook");
311312 hasCtrlDep = R->getValueAsBit("hasCtrlDep");
312313 isNotDuplicable = R->getValueAsBit("isNotDuplicable");
313314 hasSideEffects = R->getValueAsBit("hasSideEffects");
232232 bool isReMaterializable;
233233 bool hasDelaySlot;
234234 bool usesCustomInserter;
235 bool hasPostISelHook;
235236 bool hasCtrlDep;
236237 bool isNotDuplicable;
237238 bool hasSideEffects;
287287 if (Inst.isNotDuplicable) OS << "|(1<
288288 if (Inst.Operands.hasOptionalDef) OS << "|(1<
289289 if (Inst.usesCustomInserter) OS << "|(1<
290 if (Inst.hasPostISelHook) OS << "|(1<
290291 if (Inst.Operands.isVariadic)OS << "|(1<
291292 if (Inst.hasSideEffects) OS << "|(1<
292293 if (Inst.isAsCheapAsAMove) OS << "|(1<