llvm.org GIT mirror llvm / 37e5cfa
PR19320: The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP. It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524 91177308-0d34-0410-b5e6-96231b3b80d8 Stepan Dyatkovskiy 6 years ago
2 changed file(s) with 18 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
54075407 Operands.size() == 4) {
54085408 ARMOperand *Op = static_cast(Operands[2]);
54095409 assert(Op->isReg() && "expected register argument");
5410 assert(MRI->getMatchingSuperReg(Op->getReg(), ARM::gsub_0,
5411 &MRI->getRegClass(ARM::GPRPairRegClassID))
5412 && "expected register pair");
5410
5411 unsigned SuperReg = MRI->getMatchingSuperReg(
5412 Op->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5413
5414 assert(SuperReg && "expected register pair");
5415
5416 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5417
54135418 Operands.insert(Operands.begin() + 3,
5414 ARMOperand::CreateReg(Op->getReg() + 1, Op->getStartLoc(),
5419 ARMOperand::CreateReg(PairedReg, Op->getStartLoc(),
54155420 Op->getEndLoc()));
54165421 }
54175422
0 // PR19320
1 // RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
2 .text
3
4 // CHECK: ldrd r12, sp, [r0, #32] @ encoding: [0xd0,0xc2,0xc0,0xe1]
5 ldrd r12, [r0, #32]
6
7 // CHECK: strd r12, sp, [r0, #32] @ encoding: [0xf0,0xc2,0xc0,0xe1]
8 strd r12, [r0, #32]