llvm.org GIT mirror llvm / 37c9f92
Merging r311061: ------------------------------------------------------------------------ r311061 | compnerd | 2017-08-16 19:42:24 -0700 (Wed, 16 Aug 2017) | 10 lines ARM: mark CPSR as clobbered for Windows VLAs When lowering a VLA, we emit a __chstk call. However, this call can internally clobber CPSR. We did not mark this register as an ImpDef, which could potentially allow a comparison to be hoisted above the call to `__chkstk`. In such a case, the CPSR could be clobbered, and the check invalidated. When the support was initially added, it seemed that the call would take care of preventing CPSR from being clobbered, but this is not the case. Mark the register as clobbered to fix a possible state corruption. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@311461 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 2 years ago
2 changed file(s) with 17 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
88048804 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
88058805 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
88068806 .addReg(ARM::R12,
8807 RegState::Implicit | RegState::Define | RegState::Dead)
8808 .addReg(ARM::CPSR,
88078809 RegState::Implicit | RegState::Define | RegState::Dead);
88088810 break;
88098811 case CodeModel::Large:
88198821 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
88208822 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
88218823 .addReg(ARM::R12,
8824 RegState::Implicit | RegState::Define | RegState::Dead)
8825 .addReg(ARM::CPSR,
88228826 RegState::Implicit | RegState::Define | RegState::Dead);
88238827 break;
88248828 }
0 ; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null %s -print-machineinstrs=expand-isel-pseudos 2>&1 | FileCheck %s
1
2 declare arm_aapcs_vfpcc void @g(i8*) local_unnamed_addr
3
4 define arm_aapcs_vfpcc void @f(i32 %i) local_unnamed_addr {
5 entry:
6 %vla = alloca i8, i32 %i, align 1
7 call arm_aapcs_vfpcc void @g(i8* nonnull %vla)
8 ret void
9 }
10
11 ; CHECK: tBL pred:14, pred:%noreg, , %LR, %SP, %R4, %R4, %R12, %CPSR
12