llvm.org GIT mirror llvm / 374c7da
[DAGCombine] Use ConstantSDNode::getAPIntValue() instead of getZExtValue(). Use getAPIntValue() in a few more places. Most of the time getZExtValue() is fine, but occasionally there's fuzzed code or someone decides to create i65536 or something..... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363887 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 3 months ago
1 changed file(s) with 2 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
22172217 EVT VT = ShiftOp.getValueType();
22182218 SDValue ShAmt = ShiftOp.getOperand(1);
22192219 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
2220 if (!ShAmtC || ShAmtC->getZExtValue() != VT.getScalarSizeInBits() - 1)
2220 if (!ShAmtC || ShAmtC->getAPIntValue() != (VT.getScalarSizeInBits() - 1))
22212221 return SDValue();
22222222
22232223 // Eliminate the 'not' by adjusting the shift and add/sub constant:
29562956 // -(X >>s 31) -> (X >>u 31)
29572957 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
29582958 ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1));
2959 if (ShiftAmt && ShiftAmt->getZExtValue() == BitWidth - 1) {
2959 if (ShiftAmt && ShiftAmt->getAPIntValue() == (BitWidth - 1)) {
29602960 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
29612961 if (!LegalOperations || TLI.isOperationLegal(NewSh, VT))
29622962 return DAG.getNode(NewSh, DL, VT, N1.getOperand(0), N1.getOperand(1));