llvm.org GIT mirror llvm / 3745f06
[BypassSlowDivision] Improve our handling of divisions by constants (This reapplies r314253. r314253 was reverted on r314482 because of a correctness regression on P100, but that regression was identified to be something else.) Summary: Don't bail out on constant divisors for divisions that can be narrowed without introducing control flow . This gives us a 32 bit multiply instead of an emulated 64 bit multiply in the generated PTX assembly. Reviewers: jlebar Subscribers: jholewinski, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D38265 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319677 91177308-0d34-0410-b5e6-96231b3b80d8 Sanjoy Das 1 year, 11 months ago
2 changed file(s) with 90 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
351351 Value *Dividend = SlowDivOrRem->getOperand(0);
352352 Value *Divisor = SlowDivOrRem->getOperand(1);
353353
354 if (isa(Divisor)) {
355 // Keep division by a constant for DAGCombiner.
356 return None;
357 }
358
359354 VisitedSetTy SetL;
360355 ValueRange DividendRange = getValueRange(Dividend, SetL);
361356 if (DividendRange == VALRNG_LIKELY_LONG)
371366
372367 if (DividendShort && DivisorShort) {
373368 // If both operands are known to be short then just replace the long
374 // division with a short one in-place.
369 // division with a short one in-place. Since we're not introducing control
370 // flow in this case, narrowing the division is always a win, even if the
371 // divisor is a constant (and will later get replaced by a multiplication).
375372
376373 IRBuilder<> Builder(SlowDivOrRem);
377374 Value *TruncDividend = Builder.CreateTrunc(Dividend, BypassType);
381378 Value *ExtDiv = Builder.CreateZExt(TruncDiv, getSlowType());
382379 Value *ExtRem = Builder.CreateZExt(TruncRem, getSlowType());
383380 return QuotRemPair(ExtDiv, ExtRem);
384 } else if (DividendShort && !isSignedOp()) {
381 }
382
383 if (isa(Divisor)) {
384 // If the divisor is not a constant, DAGCombiner will convert it to a
385 // multiplication by a magic constant. It isn't clear if it is worth
386 // introducing control flow to get a narrower multiply.
387 return None;
388 }
389
390 if (DividendShort && !isSignedOp()) {
385391 // If the division is unsigned and Dividend is known to be short, then
386392 // either
387393 // 1) Divisor is less or equal to Dividend, and the result can be computed
2626 store i64 %d, i64* %retptr
2727 ret void
2828 }
29
30 ; CHECK-LABEL: @udiv_by_constant(
31 define i64 @udiv_by_constant(i32 %a) {
32 ; CHECK-NEXT: [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i64
33 ; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A_ZEXT]] to i32
34 ; CHECK-NEXT: [[TMP2:%.*]] = udiv i32 [[TMP1]], 50
35 ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
36 ; CHECK-NEXT: ret i64 [[TMP3]]
37
38 %a.zext = zext i32 %a to i64
39 %wide.div = udiv i64 %a.zext, 50
40 ret i64 %wide.div
41 }
42
43 ; CHECK-LABEL: @urem_by_constant(
44 define i64 @urem_by_constant(i32 %a) {
45 ; CHECK-NEXT: [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i64
46 ; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A_ZEXT]] to i32
47 ; CHECK-NEXT: [[TMP2:%.*]] = urem i32 [[TMP1]], 50
48 ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
49 ; CHECK-NEXT: ret i64 [[TMP3]]
50
51 %a.zext = zext i32 %a to i64
52 %wide.div = urem i64 %a.zext, 50
53 ret i64 %wide.div
54 }
55
56 ; Negative test: instead of emitting a runtime check on %a, we prefer to let the
57 ; DAGCombiner transform this division by constant into a multiplication (with a
58 ; "magic constant").
59 ;
60 ; CHECK-LABEL: @udiv_by_constant_negative_0(
61 define i64 @udiv_by_constant_negative_0(i64 %a) {
62 ; CHECK-NEXT: [[WIDE_DIV:%.*]] = udiv i64 [[A:%.*]], 50
63 ; CHECK-NEXT: ret i64 [[WIDE_DIV]]
64
65 %wide.div = udiv i64 %a, 50
66 ret i64 %wide.div
67 }
68
69 ; Negative test: while we know the dividend is short, the divisor isn't. This
70 ; test is here for completeness, but instcombine will optimize this to return 0.
71 ;
72 ; CHECK-LABEL: @udiv_by_constant_negative_1(
73 define i64 @udiv_by_constant_negative_1(i32 %a) {
74 ; CHECK-NEXT: [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i64
75 ; CHECK-NEXT: [[WIDE_DIV:%.*]] = udiv i64 [[A_ZEXT]], 8589934592
76 ; CHECK-NEXT: ret i64 [[WIDE_DIV]]
77
78 %a.zext = zext i32 %a to i64
79 %wide.div = udiv i64 %a.zext, 8589934592 ;; == 1 << 33
80 ret i64 %wide.div
81 }
82
83 ; URem version of udiv_by_constant_negative_0
84 ;
85 ; CHECK-LABEL: @urem_by_constant_negative_0(
86 define i64 @urem_by_constant_negative_0(i64 %a) {
87 ; CHECK-NEXT: [[WIDE_DIV:%.*]] = urem i64 [[A:%.*]], 50
88 ; CHECK-NEXT: ret i64 [[WIDE_DIV]]
89
90 %wide.div = urem i64 %a, 50
91 ret i64 %wide.div
92 }
93
94 ; URem version of udiv_by_constant_negative_1
95 ;
96 ; CHECK-LABEL: @urem_by_constant_negative_1(
97 define i64 @urem_by_constant_negative_1(i32 %a) {
98 ; CHECK-NEXT: [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i64
99 ; CHECK-NEXT: [[WIDE_DIV:%.*]] = urem i64 [[A_ZEXT]], 8589934592
100 ; CHECK-NEXT: ret i64 [[WIDE_DIV]]
101
102 %a.zext = zext i32 %a to i64
103 %wide.div = urem i64 %a.zext, 8589934592 ;; == 1 << 33
104 ret i64 %wide.div
105 }