llvm.org GIT mirror llvm / 3706c8f
Fixed max/min typo in test names git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245278 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 4 years ago
2 changed file(s) with 152 addition(s) and 152 deletion(s). Raw diff Collapse all Expand all
23932393 ret <16 x i8> %4
23942394 }
23952395
2396 define <2 x i64> @max_lt_v2i64c() {
2397 ; SSE2-LABEL: max_lt_v2i64c:
2396 define <2 x i64> @min_lt_v2i64c() {
2397 ; SSE2-LABEL: min_lt_v2i64c:
23982398 ; SSE2: # BB#0:
23992399 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551609,7]
24002400 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551615,1]
24162416 ; SSE2-NEXT: por %xmm3, %xmm0
24172417 ; SSE2-NEXT: retq
24182418 ;
2419 ; SSE41-LABEL: max_lt_v2i64c:
2419 ; SSE41-LABEL: min_lt_v2i64c:
24202420 ; SSE41: # BB#0:
24212421 ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551609,7]
24222422 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551615,1]
24362436 ; SSE41-NEXT: movapd %xmm1, %xmm0
24372437 ; SSE41-NEXT: retq
24382438 ;
2439 ; SSE42-LABEL: max_lt_v2i64c:
2439 ; SSE42-LABEL: min_lt_v2i64c:
24402440 ; SSE42: # BB#0:
24412441 ; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551609,7]
24422442 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551615,1]
24462446 ; SSE42-NEXT: movapd %xmm1, %xmm0
24472447 ; SSE42-NEXT: retq
24482448 ;
2449 ; AVX-LABEL: max_lt_v2i64c:
2449 ; AVX-LABEL: min_lt_v2i64c:
24502450 ; AVX: # BB#0:
24512451 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [18446744073709551609,7]
24522452 ; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [18446744073709551615,1]
24602460 ret <2 x i64> %4
24612461 }
24622462
2463 define <4 x i64> @max_lt_v4i64c() {
2464 ; SSE2-LABEL: max_lt_v4i64c:
2463 define <4 x i64> @min_lt_v4i64c() {
2464 ; SSE2-LABEL: min_lt_v4i64c:
24652465 ; SSE2: # BB#0:
24662466 ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [18446744073709551609,18446744073709551615]
24672467 ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [1,7]
25012501 ; SSE2-NEXT: por %xmm2, %xmm1
25022502 ; SSE2-NEXT: retq
25032503 ;
2504 ; SSE41-LABEL: max_lt_v4i64c:
2504 ; SSE41-LABEL: min_lt_v4i64c:
25052505 ; SSE41: # BB#0:
25062506 ; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [18446744073709551609,18446744073709551615]
25072507 ; SSE41-NEXT: movdqa {{.*#+}} xmm8 = [1,7]
25372537 ; SSE41-NEXT: movapd %xmm2, %xmm0
25382538 ; SSE41-NEXT: retq
25392539 ;
2540 ; SSE42-LABEL: max_lt_v4i64c:
2540 ; SSE42-LABEL: min_lt_v4i64c:
25412541 ; SSE42: # BB#0:
25422542 ; SSE42-NEXT: movdqa {{.*#+}} xmm4 = [18446744073709551609,18446744073709551615]
25432543 ; SSE42-NEXT: movdqa {{.*#+}} xmm5 = [1,7]
25532553 ; SSE42-NEXT: movapd %xmm2, %xmm0
25542554 ; SSE42-NEXT: retq
25552555 ;
2556 ; AVX1-LABEL: max_lt_v4i64c:
2556 ; AVX1-LABEL: min_lt_v4i64c:
25572557 ; AVX1: # BB#0:
25582558 ; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
25592559 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [18446744073709551615,18446744073709551609]
25642564 ; AVX1-NEXT: vblendvpd %ymm1, {{.*}}(%rip), %ymm0, %ymm0
25652565 ; AVX1-NEXT: retq
25662566 ;
2567 ; AVX2-LABEL: max_lt_v4i64c:
2567 ; AVX2-LABEL: min_lt_v4i64c:
25682568 ; AVX2: # BB#0:
25692569 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [18446744073709551609,18446744073709551615,1,7]
25702570 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [18446744073709551615,18446744073709551609,7,1]
25722572 ; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
25732573 ; AVX2-NEXT: retq
25742574 ;
2575 ; AVX512-LABEL: max_lt_v4i64c:
2575 ; AVX512-LABEL: min_lt_v4i64c:
25762576 ; AVX512: # BB#0:
25772577 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [18446744073709551609,18446744073709551615,1,7]
25782578 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm1 = [18446744073709551615,18446744073709551609,7,1]
25862586 ret <4 x i64> %4
25872587 }
25882588
2589 define <4 x i32> @max_lt_v4i32c() {
2590 ; SSE2-LABEL: max_lt_v4i32c:
2589 define <4 x i32> @min_lt_v4i32c() {
2590 ; SSE2-LABEL: min_lt_v4i32c:
25912591 ; SSE2: # BB#0:
25922592 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [4294967289,4294967295,1,7]
25932593 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,4294967289,7,1]
25982598 ; SSE2-NEXT: por %xmm1, %xmm0
25992599 ; SSE2-NEXT: retq
26002600 ;
2601 ; SSE41-LABEL: max_lt_v4i32c:
2601 ; SSE41-LABEL: min_lt_v4i32c:
26022602 ; SSE41: # BB#0:
26032603 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
26042604 ; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm0
26052605 ; SSE41-NEXT: retq
26062606 ;
2607 ; SSE42-LABEL: max_lt_v4i32c:
2607 ; SSE42-LABEL: min_lt_v4i32c:
26082608 ; SSE42: # BB#0:
26092609 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
26102610 ; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm0
26112611 ; SSE42-NEXT: retq
26122612 ;
2613 ; AVX-LABEL: max_lt_v4i32c:
2613 ; AVX-LABEL: min_lt_v4i32c:
26142614 ; AVX: # BB#0:
26152615 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
26162616 ; AVX-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
26222622 ret <4 x i32> %4
26232623 }
26242624
2625 define <8 x i32> @max_lt_v8i32c() {
2626 ; SSE2-LABEL: max_lt_v8i32c:
2625 define <8 x i32> @min_lt_v8i32c() {
2626 ; SSE2-LABEL: min_lt_v8i32c:
26272627 ; SSE2: # BB#0:
26282628 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [4294967289,4294967291,4294967293,4294967295]
26292629 ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [1,3,5,7]
26412641 ; SSE2-NEXT: por %xmm3, %xmm1
26422642 ; SSE2-NEXT: retq
26432643 ;
2644 ; SSE41-LABEL: max_lt_v8i32c:
2644 ; SSE41-LABEL: min_lt_v8i32c:
26452645 ; SSE41: # BB#0:
26462646 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
26472647 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
26492649 ; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm1
26502650 ; SSE41-NEXT: retq
26512651 ;
2652 ; SSE42-LABEL: max_lt_v8i32c:
2652 ; SSE42-LABEL: min_lt_v8i32c:
26532653 ; SSE42: # BB#0:
26542654 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
26552655 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
26572657 ; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm1
26582658 ; SSE42-NEXT: retq
26592659 ;
2660 ; AVX1-LABEL: max_lt_v8i32c:
2660 ; AVX1-LABEL: min_lt_v8i32c:
26612661 ; AVX1: # BB#0:
26622662 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
26632663 ; AVX1-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
26662666 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
26672667 ; AVX1-NEXT: retq
26682668 ;
2669 ; AVX2-LABEL: max_lt_v8i32c:
2669 ; AVX2-LABEL: min_lt_v8i32c:
26702670 ; AVX2: # BB#0:
26712671 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
26722672 ; AVX2-NEXT: vpminsd {{.*}}(%rip), %ymm0, %ymm0
26732673 ; AVX2-NEXT: retq
26742674 ;
2675 ; AVX512-LABEL: max_lt_v8i32c:
2675 ; AVX512-LABEL: min_lt_v8i32c:
26762676 ; AVX512: # BB#0:
26772677 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
26782678 ; AVX512-NEXT: vpminsd {{.*}}(%rip), %ymm0, %ymm0
26842684 ret <8 x i32> %4
26852685 }
26862686
2687 define <8 x i16> @max_lt_v8i16c() {
2688 ; SSE-LABEL: max_lt_v8i16c:
2687 define <8 x i16> @min_lt_v8i16c() {
2688 ; SSE-LABEL: min_lt_v8i16c:
26892689 ; SSE: # BB#0:
26902690 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
26912691 ; SSE-NEXT: pminsw {{.*}}(%rip), %xmm0
26922692 ; SSE-NEXT: retq
26932693 ;
2694 ; AVX-LABEL: max_lt_v8i16c:
2694 ; AVX-LABEL: min_lt_v8i16c:
26952695 ; AVX: # BB#0:
26962696 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
26972697 ; AVX-NEXT: vpminsw {{.*}}(%rip), %xmm0, %xmm0
27032703 ret <8 x i16> %4
27042704 }
27052705
2706 define <16 x i16> @max_lt_v16i16c() {
2707 ; SSE-LABEL: max_lt_v16i16c:
2706 define <16 x i16> @min_lt_v16i16c() {
2707 ; SSE-LABEL: min_lt_v16i16c:
27082708 ; SSE: # BB#0:
27092709 ; SSE-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
27102710 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
27122712 ; SSE-NEXT: pminsw {{.*}}(%rip), %xmm1
27132713 ; SSE-NEXT: retq
27142714 ;
2715 ; AVX1-LABEL: max_lt_v16i16c:
2715 ; AVX1-LABEL: min_lt_v16i16c:
27162716 ; AVX1: # BB#0:
27172717 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
27182718 ; AVX1-NEXT: vpminsw {{.*}}(%rip), %xmm0, %xmm0
27212721 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
27222722 ; AVX1-NEXT: retq
27232723 ;
2724 ; AVX2-LABEL: max_lt_v16i16c:
2724 ; AVX2-LABEL: min_lt_v16i16c:
27252725 ; AVX2: # BB#0:
27262726 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
27272727 ; AVX2-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
27282728 ; AVX2-NEXT: retq
27292729 ;
2730 ; AVX512-LABEL: max_lt_v16i16c:
2730 ; AVX512-LABEL: min_lt_v16i16c:
27312731 ; AVX512: # BB#0:
27322732 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
27332733 ; AVX512-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
27392739 ret <16 x i16> %4
27402740 }
27412741
2742 define <16 x i8> @max_lt_v16i8c() {
2743 ; SSE2-LABEL: max_lt_v16i8c:
2742 define <16 x i8> @min_lt_v16i8c() {
2743 ; SSE2-LABEL: min_lt_v16i8c:
27442744 ; SSE2: # BB#0:
27452745 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
27462746 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,254,253,252,251,250,249,0,7,6,5,4,3,2,1,0]
27512751 ; SSE2-NEXT: por %xmm1, %xmm0
27522752 ; SSE2-NEXT: retq
27532753 ;
2754 ; SSE41-LABEL: max_lt_v16i8c:
2754 ; SSE41-LABEL: min_lt_v16i8c:
27552755 ; SSE41: # BB#0:
27562756 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
27572757 ; SSE41-NEXT: pminsb {{.*}}(%rip), %xmm0
27582758 ; SSE41-NEXT: retq
27592759 ;
2760 ; SSE42-LABEL: max_lt_v16i8c:
2760 ; SSE42-LABEL: min_lt_v16i8c:
27612761 ; SSE42: # BB#0:
27622762 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
27632763 ; SSE42-NEXT: pminsb {{.*}}(%rip), %xmm0
27642764 ; SSE42-NEXT: retq
27652765 ;
2766 ; AVX-LABEL: max_lt_v16i8c:
2766 ; AVX-LABEL: min_lt_v16i8c:
27672767 ; AVX: # BB#0:
27682768 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
27692769 ; AVX-NEXT: vpminsb {{.*}}(%rip), %xmm0, %xmm0
27752775 ret <16 x i8> %4
27762776 }
27772777
2778 define <2 x i64> @max_le_v2i64c() {
2779 ; SSE2-LABEL: max_le_v2i64c:
2778 define <2 x i64> @min_le_v2i64c() {
2779 ; SSE2-LABEL: min_le_v2i64c:
27802780 ; SSE2: # BB#0:
27812781 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551609,7]
27822782 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551615,1]
27992799 ; SSE2-NEXT: por %xmm3, %xmm0
28002800 ; SSE2-NEXT: retq
28012801 ;
2802 ; SSE41-LABEL: max_le_v2i64c:
2802 ; SSE41-LABEL: min_le_v2i64c:
28032803 ; SSE41: # BB#0:
28042804 ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551609,7]
28052805 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551615,1]
28212821 ; SSE41-NEXT: movapd %xmm1, %xmm0
28222822 ; SSE41-NEXT: retq
28232823 ;
2824 ; SSE42-LABEL: max_le_v2i64c:
2824 ; SSE42-LABEL: min_le_v2i64c:
28252825 ; SSE42: # BB#0:
28262826 ; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551609,7]
28272827 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551615,1]
28332833 ; SSE42-NEXT: movapd %xmm1, %xmm0
28342834 ; SSE42-NEXT: retq
28352835 ;
2836 ; AVX-LABEL: max_le_v2i64c:
2836 ; AVX-LABEL: min_le_v2i64c:
28372837 ; AVX: # BB#0:
28382838 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [18446744073709551609,7]
28392839 ; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [18446744073709551615,1]
28492849 ret <2 x i64> %4
28502850 }
28512851
2852 define <4 x i64> @max_le_v4i64c() {
2853 ; SSE2-LABEL: max_le_v4i64c:
2852 define <4 x i64> @min_le_v4i64c() {
2853 ; SSE2-LABEL: min_le_v4i64c:
28542854 ; SSE2: # BB#0:
28552855 ; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [18446744073709551609,18446744073709551615]
28562856 ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [1,7]
28922892 ; SSE2-NEXT: por %xmm6, %xmm1
28932893 ; SSE2-NEXT: retq
28942894 ;
2895 ; SSE41-LABEL: max_le_v4i64c:
2895 ; SSE41-LABEL: min_le_v4i64c:
28962896 ; SSE41: # BB#0:
28972897 ; SSE41-NEXT: movdqa {{.*#+}} xmm9 = [18446744073709551609,18446744073709551615]
28982898 ; SSE41-NEXT: movdqa {{.*#+}} xmm8 = [1,7]
29312931 ; SSE41-NEXT: movapd %xmm2, %xmm0
29322932 ; SSE41-NEXT: retq
29332933 ;
2934 ; SSE42-LABEL: max_le_v4i64c:
2934 ; SSE42-LABEL: min_le_v4i64c:
29352935 ; SSE42: # BB#0:
29362936 ; SSE42-NEXT: movdqa {{.*#+}} xmm4 = [18446744073709551609,18446744073709551615]
29372937 ; SSE42-NEXT: movdqa {{.*#+}} xmm5 = [1,7]
29502950 ; SSE42-NEXT: movapd %xmm2, %xmm0
29512951 ; SSE42-NEXT: retq
29522952 ;
2953 ; AVX1-LABEL: max_le_v4i64c:
2953 ; AVX1-LABEL: min_le_v4i64c:
29542954 ; AVX1: # BB#0:
29552955 ; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
29562956 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,7]
29642964 ; AVX1-NEXT: vblendvpd %ymm1, {{.*}}(%rip), %ymm0, %ymm0
29652965 ; AVX1-NEXT: retq
29662966 ;
2967 ; AVX2-LABEL: max_le_v4i64c:
2967 ; AVX2-LABEL: min_le_v4i64c:
29682968 ; AVX2: # BB#0:
29692969 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [18446744073709551609,18446744073709551615,1,7]
29702970 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [18446744073709551615,18446744073709551609,7,1]
29742974 ; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
29752975 ; AVX2-NEXT: retq
29762976 ;
2977 ; AVX512-LABEL: max_le_v4i64c:
2977 ; AVX512-LABEL: min_le_v4i64c:
29782978 ; AVX512: # BB#0:
29792979 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [18446744073709551609,18446744073709551615,1,7]
29802980 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm1 = [18446744073709551615,18446744073709551609,7,1]
29902990 ret <4 x i64> %4
29912991 }
29922992
2993 define <4 x i32> @max_le_v4i32c() {
2994 ; SSE2-LABEL: max_le_v4i32c:
2993 define <4 x i32> @min_le_v4i32c() {
2994 ; SSE2-LABEL: min_le_v4i32c:
29952995 ; SSE2: # BB#0:
29962996 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [4294967289,4294967295,1,7]
29972997 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,4294967289,7,1]
30043004 ; SSE2-NEXT: por %xmm3, %xmm0
30053005 ; SSE2-NEXT: retq
30063006 ;
3007 ; SSE41-LABEL: max_le_v4i32c:
3007 ; SSE41-LABEL: min_le_v4i32c:
30083008 ; SSE41: # BB#0:
30093009 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
30103010 ; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm0
30113011 ; SSE41-NEXT: retq
30123012 ;
3013 ; SSE42-LABEL: max_le_v4i32c:
3013 ; SSE42-LABEL: min_le_v4i32c:
30143014 ; SSE42: # BB#0:
30153015 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
30163016 ; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm0
30173017 ; SSE42-NEXT: retq
30183018 ;
3019 ; AVX-LABEL: max_le_v4i32c:
3019 ; AVX-LABEL: min_le_v4i32c:
30203020 ; AVX: # BB#0:
30213021 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
30223022 ; AVX-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
30283028 ret <4 x i32> %4
30293029 }
30303030
3031 define <8 x i32> @max_le_v8i32c() {
3032 ; SSE2-LABEL: max_le_v8i32c:
3031 define <8 x i32> @min_le_v8i32c() {
3032 ; SSE2-LABEL: min_le_v8i32c:
30333033 ; SSE2: # BB#0:
30343034 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [4294967289,4294967291,4294967293,4294967295]
30353035 ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [1,3,5,7]
30513051 ; SSE2-NEXT: por %xmm6, %xmm1
30523052 ; SSE2-NEXT: retq
30533053 ;
3054 ; SSE41-LABEL: max_le_v8i32c:
3054 ; SSE41-LABEL: min_le_v8i32c:
30553055 ; SSE41: # BB#0:
30563056 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
30573057 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
30593059 ; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm1
30603060 ; SSE41-NEXT: retq
30613061 ;
3062 ; SSE42-LABEL: max_le_v8i32c:
3062 ; SSE42-LABEL: min_le_v8i32c:
30633063 ; SSE42: # BB#0:
30643064 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
30653065 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
30673067 ; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm1
30683068 ; SSE42-NEXT: retq
30693069 ;
3070 ; AVX1-LABEL: max_le_v8i32c:
3070 ; AVX1-LABEL: min_le_v8i32c:
30713071 ; AVX1: # BB#0:
30723072 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
30733073 ; AVX1-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
30763076 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
30773077 ; AVX1-NEXT: retq
30783078 ;
3079 ; AVX2-LABEL: max_le_v8i32c:
3079 ; AVX2-LABEL: min_le_v8i32c:
30803080 ; AVX2: # BB#0:
30813081 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
30823082 ; AVX2-NEXT: vpminsd {{.*}}(%rip), %ymm0, %ymm0
30833083 ; AVX2-NEXT: retq
30843084 ;
3085 ; AVX512-LABEL: max_le_v8i32c:
3085 ; AVX512-LABEL: min_le_v8i32c:
30863086 ; AVX512: # BB#0:
30873087 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
30883088 ; AVX512-NEXT: vpminsd {{.*}}(%rip), %ymm0, %ymm0
30943094 ret <8 x i32> %4
30953095 }
30963096
3097 define <8 x i16> @max_le_v8i16c() {
3098 ; SSE-LABEL: max_le_v8i16c:
3097 define <8 x i16> @min_le_v8i16c() {
3098 ; SSE-LABEL: min_le_v8i16c:
30993099 ; SSE: # BB#0:
31003100 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
31013101 ; SSE-NEXT: pminsw {{.*}}(%rip), %xmm0
31023102 ; SSE-NEXT: retq
31033103 ;
3104 ; AVX-LABEL: max_le_v8i16c:
3104 ; AVX-LABEL: min_le_v8i16c:
31053105 ; AVX: # BB#0:
31063106 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
31073107 ; AVX-NEXT: vpminsw {{.*}}(%rip), %xmm0, %xmm0
31133113 ret <8 x i16> %4
31143114 }
31153115
3116 define <16 x i16> @max_le_v16i16c() {
3117 ; SSE-LABEL: max_le_v16i16c:
3116 define <16 x i16> @min_le_v16i16c() {
3117 ; SSE-LABEL: min_le_v16i16c:
31183118 ; SSE: # BB#0:
31193119 ; SSE-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
31203120 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
31223122 ; SSE-NEXT: pminsw {{.*}}(%rip), %xmm1
31233123 ; SSE-NEXT: retq
31243124 ;
3125 ; AVX1-LABEL: max_le_v16i16c:
3125 ; AVX1-LABEL: min_le_v16i16c:
31263126 ; AVX1: # BB#0:
31273127 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
31283128 ; AVX1-NEXT: vpminsw {{.*}}(%rip), %xmm0, %xmm0
31313131 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
31323132 ; AVX1-NEXT: retq
31333133 ;
3134 ; AVX2-LABEL: max_le_v16i16c:
3134 ; AVX2-LABEL: min_le_v16i16c:
31353135 ; AVX2: # BB#0:
31363136 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
31373137 ; AVX2-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
31383138 ; AVX2-NEXT: retq
31393139 ;
3140 ; AVX512-LABEL: max_le_v16i16c:
3140 ; AVX512-LABEL: min_le_v16i16c:
31413141 ; AVX512: # BB#0:
31423142 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
31433143 ; AVX512-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
31493149 ret <16 x i16> %4
31503150 }
31513151
3152 define <16 x i8> @max_le_v16i8c() {
3153 ; SSE2-LABEL: max_le_v16i8c:
3152 define <16 x i8> @min_le_v16i8c() {
3153 ; SSE2-LABEL: min_le_v16i8c:
31543154 ; SSE2: # BB#0:
31553155 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
31563156 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,254,253,252,251,250,249,0,7,6,5,4,3,2,1,0]
31633163 ; SSE2-NEXT: por %xmm3, %xmm0
31643164 ; SSE2-NEXT: retq
31653165 ;
3166 ; SSE41-LABEL: max_le_v16i8c:
3166 ; SSE41-LABEL: min_le_v16i8c:
31673167 ; SSE41: # BB#0:
31683168 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
31693169 ; SSE41-NEXT: pminsb {{.*}}(%rip), %xmm0
31703170 ; SSE41-NEXT: retq
31713171 ;
3172 ; SSE42-LABEL: max_le_v16i8c:
3172 ; SSE42-LABEL: min_le_v16i8c:
31733173 ; SSE42: # BB#0:
31743174 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
31753175 ; SSE42-NEXT: pminsb {{.*}}(%rip), %xmm0
31763176 ; SSE42-NEXT: retq
31773177 ;
3178 ; AVX-LABEL: max_le_v16i8c:
3178 ; AVX-LABEL: min_le_v16i8c:
31793179 ; AVX: # BB#0:
31803180 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
31813181 ; AVX-NEXT: vpminsb {{.*}}(%rip), %xmm0, %xmm0
25692569 ret <16 x i8> %4
25702570 }
25712571
2572 define <2 x i64> @max_lt_v2i64c() {
2573 ; SSE2-LABEL: max_lt_v2i64c:
2572 define <2 x i64> @min_lt_v2i64c() {
2573 ; SSE2-LABEL: min_lt_v2i64c:
25742574 ; SSE2: # BB#0:
25752575 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551609,7]
25762576 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551615,1]
25922592 ; SSE2-NEXT: por %xmm3, %xmm0
25932593 ; SSE2-NEXT: retq
25942594 ;
2595 ; SSE41-LABEL: max_lt_v2i64c:
2595 ; SSE41-LABEL: min_lt_v2i64c:
25962596 ; SSE41: # BB#0:
25972597 ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551609,7]
25982598 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551615,1]
26122612 ; SSE41-NEXT: movapd %xmm1, %xmm0
26132613 ; SSE41-NEXT: retq
26142614 ;
2615 ; SSE42-LABEL: max_lt_v2i64c:
2615 ; SSE42-LABEL: min_lt_v2i64c:
26162616 ; SSE42: # BB#0:
26172617 ; SSE42-NEXT: movapd {{.*#+}} xmm1 = [18446744073709551615,1]
26182618 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775807,9223372036854775809]
26212621 ; SSE42-NEXT: movapd %xmm1, %xmm0
26222622 ; SSE42-NEXT: retq
26232623 ;
2624 ; AVX-LABEL: max_lt_v2i64c:
2624 ; AVX-LABEL: min_lt_v2i64c:
26252625 ; AVX: # BB#0:
26262626 ; AVX-NEXT: vmovapd {{.*#+}} xmm0 = [18446744073709551615,1]
26272627 ; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775807,9223372036854775809]
26352635 ret <2 x i64> %4
26362636 }
26372637
2638 define <4 x i64> @max_lt_v4i64c() {
2639 ; SSE2-LABEL: max_lt_v4i64c:
2638 define <4 x i64> @min_lt_v4i64c() {
2639 ; SSE2-LABEL: min_lt_v4i64c:
26402640 ; SSE2: # BB#0:
26412641 ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [18446744073709551609,18446744073709551615]
26422642 ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [1,7]
26762676 ; SSE2-NEXT: por %xmm2, %xmm1
26772677 ; SSE2-NEXT: retq
26782678 ;
2679 ; SSE41-LABEL: max_lt_v4i64c:
2679 ; SSE41-LABEL: min_lt_v4i64c:
26802680 ; SSE41: # BB#0:
26812681 ; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [18446744073709551609,18446744073709551615]
26822682 ; SSE41-NEXT: movdqa {{.*#+}} xmm8 = [1,7]
27122712 ; SSE41-NEXT: movapd %xmm2, %xmm0
27132713 ; SSE41-NEXT: retq
27142714 ;
2715 ; SSE42-LABEL: max_lt_v4i64c:
2715 ; SSE42-LABEL: min_lt_v4i64c:
27162716 ; SSE42: # BB#0:
27172717 ; SSE42-NEXT: movapd {{.*#+}} xmm1 = [7,1]
27182718 ; SSE42-NEXT: movapd {{.*#+}} xmm2 = [18446744073709551615,18446744073709551609]
27262726 ; SSE42-NEXT: movapd %xmm2, %xmm0
27272727 ; SSE42-NEXT: retq
27282728 ;
2729 ; AVX1-LABEL: max_lt_v4i64c:
2729 ; AVX1-LABEL: min_lt_v4i64c:
27302730 ; AVX1: # BB#0:
27312731 ; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
27322732 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775807,9223372036854775801]
27372737 ; AVX1-NEXT: vblendvpd %ymm1, {{.*}}(%rip), %ymm0, %ymm0
27382738 ; AVX1-NEXT: retq
27392739 ;
2740 ; AVX2-LABEL: max_lt_v4i64c:
2740 ; AVX2-LABEL: min_lt_v4i64c:
27412741 ; AVX2: # BB#0:
27422742 ; AVX2-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
27432743 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [9223372036854775807,9223372036854775801,9223372036854775815,9223372036854775809]
27452745 ; AVX2-NEXT: vblendvpd %ymm1, {{.*}}(%rip), %ymm0, %ymm0
27462746 ; AVX2-NEXT: retq
27472747 ;
2748 ; AVX512-LABEL: max_lt_v4i64c:
2748 ; AVX512-LABEL: min_lt_v4i64c:
27492749 ; AVX512: # BB#0:
27502750 ; AVX512-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
27512751 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm1 = [9223372036854775807,9223372036854775801,9223372036854775815,9223372036854775809]
27592759 ret <4 x i64> %4
27602760 }
27612761
2762 define <4 x i32> @max_lt_v4i32c() {
2763 ; SSE2-LABEL: max_lt_v4i32c:
2762 define <4 x i32> @min_lt_v4i32c() {
2763 ; SSE2-LABEL: min_lt_v4i32c:
27642764 ; SSE2: # BB#0:
27652765 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [2147483649,2147483641,2147483655,2147483649]
27662766 ; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
27702770 ; SSE2-NEXT: por %xmm1, %xmm0
27712771 ; SSE2-NEXT: retq
27722772 ;
2773 ; SSE41-LABEL: max_lt_v4i32c:
2773 ; SSE41-LABEL: min_lt_v4i32c:
27742774 ; SSE41: # BB#0:
27752775 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
27762776 ; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
27772777 ; SSE41-NEXT: retq
27782778 ;
2779 ; SSE42-LABEL: max_lt_v4i32c:
2779 ; SSE42-LABEL: min_lt_v4i32c:
27802780 ; SSE42: # BB#0:
27812781 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
27822782 ; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
27832783 ; SSE42-NEXT: retq
27842784 ;
2785 ; AVX-LABEL: max_lt_v4i32c:
2785 ; AVX-LABEL: min_lt_v4i32c:
27862786 ; AVX: # BB#0:
27872787 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
27882788 ; AVX-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
27942794 ret <4 x i32> %4
27952795 }
27962796
2797 define <8 x i32> @max_lt_v8i32c() {
2798 ; SSE2-LABEL: max_lt_v8i32c:
2797 define <8 x i32> @min_lt_v8i32c() {
2798 ; SSE2-LABEL: min_lt_v8i32c:
27992799 ; SSE2: # BB#0:
28002800 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483655,2147483653,2147483651,2147483649]
28012801 ; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
28112811 ; SSE2-NEXT: por %xmm2, %xmm1
28122812 ; SSE2-NEXT: retq
28132813 ;
2814 ; SSE41-LABEL: max_lt_v8i32c:
2814 ; SSE41-LABEL: min_lt_v8i32c:
28152815 ; SSE41: # BB#0:
28162816 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
28172817 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
28192819 ; SSE41-NEXT: pminud {{.*}}(%rip), %xmm1
28202820 ; SSE41-NEXT: retq
28212821 ;
2822 ; SSE42-LABEL: max_lt_v8i32c:
2822 ; SSE42-LABEL: min_lt_v8i32c:
28232823 ; SSE42: # BB#0:
28242824 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
28252825 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
28272827 ; SSE42-NEXT: pminud {{.*}}(%rip), %xmm1
28282828 ; SSE42-NEXT: retq
28292829 ;
2830 ; AVX1-LABEL: max_lt_v8i32c:
2830 ; AVX1-LABEL: min_lt_v8i32c:
28312831 ; AVX1: # BB#0:
28322832 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
28332833 ; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
28362836 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
28372837 ; AVX1-NEXT: retq
28382838 ;
2839 ; AVX2-LABEL: max_lt_v8i32c:
2839 ; AVX2-LABEL: min_lt_v8i32c:
28402840 ; AVX2: # BB#0:
28412841 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
28422842 ; AVX2-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
28432843 ; AVX2-NEXT: retq
28442844 ;
2845 ; AVX512-LABEL: max_lt_v8i32c:
2845 ; AVX512-LABEL: min_lt_v8i32c:
28462846 ; AVX512: # BB#0:
28472847 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
28482848 ; AVX512-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
28542854 ret <8 x i32> %4
28552855 }
28562856
2857 define <8 x i16> @max_lt_v8i16c() {
2858 ; SSE2-LABEL: max_lt_v8i16c:
2857 define <8 x i16> @min_lt_v8i16c() {
2858 ; SSE2-LABEL: min_lt_v8i16c:
28592859 ; SSE2: # BB#0:
28602860 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65529,65531,65533,65535,1,3,5,7]
28612861 ; SSE2-NEXT: movdqa %xmm1, %xmm2
28672867 ; SSE2-NEXT: por %xmm1, %xmm0
28682868 ; SSE2-NEXT: retq
28692869 ;
2870 ; SSE41-LABEL: max_lt_v8i16c:
2870 ; SSE41-LABEL: min_lt_v8i16c:
28712871 ; SSE41: # BB#0:
28722872 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
28732873 ; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
28742874 ; SSE41-NEXT: retq
28752875 ;
2876 ; SSE42-LABEL: max_lt_v8i16c:
2876 ; SSE42-LABEL: min_lt_v8i16c:
28772877 ; SSE42: # BB#0:
28782878 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
28792879 ; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
28802880 ; SSE42-NEXT: retq
28812881 ;
2882 ; AVX-LABEL: max_lt_v8i16c:
2882 ; AVX-LABEL: min_lt_v8i16c:
28832883 ; AVX: # BB#0:
28842884 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
28852885 ; AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
28912891 ret <8 x i16> %4
28922892 }
28932893
2894 define <16 x i16> @max_lt_v16i16c() {
2895 ; SSE2-LABEL: max_lt_v16i16c:
2894 define <16 x i16> @min_lt_v16i16c() {
2895 ; SSE2-LABEL: min_lt_v16i16c:
28962896 ; SSE2: # BB#0:
28972897 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [32775,32774,32773,32772,32771,32770,32769,32768]
28982898 ; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm1
29082908 ; SSE2-NEXT: por %xmm2, %xmm1
29092909 ; SSE2-NEXT: retq
29102910 ;
2911 ; SSE41-LABEL: max_lt_v16i16c:
2911 ; SSE41-LABEL: min_lt_v16i16c:
29122912 ; SSE41: # BB#0:
29132913 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
29142914 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
29162916 ; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm1
29172917 ; SSE41-NEXT: retq
29182918 ;
2919 ; SSE42-LABEL: max_lt_v16i16c:
2919 ; SSE42-LABEL: min_lt_v16i16c:
29202920 ; SSE42: # BB#0:
29212921 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
29222922 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
29242924 ; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm1
29252925 ; SSE42-NEXT: retq
29262926 ;
2927 ; AVX1-LABEL: max_lt_v16i16c:
2927 ; AVX1-LABEL: min_lt_v16i16c:
29282928 ; AVX1: # BB#0:
29292929 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
29302930 ; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
29332933 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
29342934 ; AVX1-NEXT: retq
29352935 ;
2936 ; AVX2-LABEL: max_lt_v16i16c:
2936 ; AVX2-LABEL: min_lt_v16i16c:
29372937 ; AVX2: # BB#0:
29382938 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
29392939 ; AVX2-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
29402940 ; AVX2-NEXT: retq
29412941 ;
2942 ; AVX512-LABEL: max_lt_v16i16c:
2942 ; AVX512-LABEL: min_lt_v16i16c:
29432943 ; AVX512: # BB#0:
29442944 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
29452945 ; AVX512-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
29512951 ret <16 x i16> %4
29522952 }
29532953
2954 define <16 x i8> @max_lt_v16i8c() {
2955 ; SSE-LABEL: max_lt_v16i8c:
2954 define <16 x i8> @min_lt_v16i8c() {
2955 ; SSE-LABEL: min_lt_v16i8c:
29562956 ; SSE: # BB#0:
29572957 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
29582958 ; SSE-NEXT: pminub {{.*}}(%rip), %xmm0
29592959 ; SSE-NEXT: retq
29602960 ;
2961 ; AVX-LABEL: max_lt_v16i8c:
2961 ; AVX-LABEL: min_lt_v16i8c:
29622962 ; AVX: # BB#0:
29632963 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
29642964 ; AVX-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm0
29702970 ret <16 x i8> %4
29712971 }
29722972
2973 define <2 x i64> @max_le_v2i64c() {
2974 ; SSE2-LABEL: max_le_v2i64c:
2973 define <2 x i64> @min_le_v2i64c() {
2974 ; SSE2-LABEL: min_le_v2i64c:
29752975 ; SSE2: # BB#0:
29762976 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551609,7]
29772977 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551615,1]
29942994 ; SSE2-NEXT: por %xmm3, %xmm0
29952995 ; SSE2-NEXT: retq
29962996 ;
2997 ; SSE41-LABEL: max_le_v2i64c:
2997 ; SSE41-LABEL: min_le_v2i64c:
29982998 ; SSE41: # BB#0:
29992999 ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551609,7]
30003000 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551615,1]
30163016 ; SSE41-NEXT: movapd %xmm1, %xmm0
30173017 ; SSE41-NEXT: retq
30183018 ;
3019 ; SSE42-LABEL: max_le_v2i64c:
3019 ; SSE42-LABEL: min_le_v2i64c:
30203020 ; SSE42: # BB#0:
30213021 ; SSE42-NEXT: movapd {{.*#+}} xmm1 = [18446744073709551615,1]
30223022 ; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775801,9223372036854775815]
30273027 ; SSE42-NEXT: movapd %xmm1, %xmm0
30283028 ; SSE42-NEXT: retq
30293029 ;
3030 ; AVX-LABEL: max_le_v2i64c:
3030 ; AVX-LABEL: min_le_v2i64c:
30313031 ; AVX: # BB#0:
30323032 ; AVX-NEXT: vmovapd {{.*#+}} xmm0 = [18446744073709551615,1]
30333033 ; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775801,9223372036854775815]
30433043 ret <2 x i64> %4
30443044 }
30453045
3046 define <4 x i64> @max_le_v4i64c() {
3047 ; SSE2-LABEL: max_le_v4i64c:
3046 define <4 x i64> @min_le_v4i64c() {
3047 ; SSE2-LABEL: min_le_v4i64c:
30483048 ; SSE2: # BB#0:
30493049 ; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [18446744073709551609,18446744073709551615]
30503050 ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [1,7]
30863086 ; SSE2-NEXT: por %xmm6, %xmm1
30873087 ; SSE2-NEXT: retq
30883088 ;
3089 ; SSE41-LABEL: max_le_v4i64c:
3089 ; SSE41-LABEL: min_le_v4i64c:
30903090 ; SSE41: # BB#0:
30913091 ; SSE41-NEXT: movdqa {{.*#+}} xmm9 = [18446744073709551609,18446744073709551615]
30923092 ; SSE41-NEXT: movdqa {{.*#+}} xmm8 = [1,7]
31253125 ; SSE41-NEXT: movapd %xmm2, %xmm0
31263126 ; SSE41-NEXT: retq
31273127 ;
3128 ; SSE42-LABEL: max_le_v4i64c:
3128 ; SSE42-LABEL: min_le_v4i64c:
31293129 ; SSE42: # BB#0:
31303130 ; SSE42-NEXT: movapd {{.*#+}} xmm1 = [7,1]
31313131 ; SSE42-NEXT: movapd {{.*#+}} xmm2 = [18446744073709551615,18446744073709551609]
31423142 ; SSE42-NEXT: movapd %xmm2, %xmm0
31433143 ; SSE42-NEXT: retq
31443144 ;
3145 ; AVX1-LABEL: max_le_v4i64c:
3145 ; AVX1-LABEL: min_le_v4i64c:
31463146 ; AVX1: # BB#0:
31473147 ; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
31483148 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775809,9223372036854775815]
31563156 ; AVX1-NEXT: vblendvpd %ymm1, {{.*}}(%rip), %ymm0, %ymm0
31573157 ; AVX1-NEXT: retq
31583158 ;
3159 ; AVX2-LABEL: max_le_v4i64c:
3159 ; AVX2-LABEL: min_le_v4i64c:
31603160 ; AVX2: # BB#0:
31613161 ; AVX2-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
31623162 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [9223372036854775801,9223372036854775807,9223372036854775809,9223372036854775815]
31663166 ; AVX2-NEXT: vblendvpd %ymm1, {{.*}}(%rip), %ymm0, %ymm0
31673167 ; AVX2-NEXT: retq
31683168 ;
3169 ; AVX512-LABEL: max_le_v4i64c:
3169 ; AVX512-LABEL: min_le_v4i64c:
31703170 ; AVX512: # BB#0:
31713171 ; AVX512-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
31723172 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm1 = [9223372036854775801,9223372036854775807,9223372036854775809,9223372036854775815]
31823182 ret <4 x i64> %4
31833183 }
31843184
3185 define <4 x i32> @max_le_v4i32c() {
3186 ; SSE2-LABEL: max_le_v4i32c:
3185 define <4 x i32> @min_le_v4i32c() {
3186 ; SSE2-LABEL: min_le_v4i32c:
31873187 ; SSE2: # BB#0:
31883188 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [2147483641,2147483647,2147483649,2147483655]
31893189 ; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
31943194 ; SSE2-NEXT: por %xmm1, %xmm0
31953195 ; SSE2-NEXT: retq
31963196 ;
3197 ; SSE41-LABEL: max_le_v4i32c:
3197 ; SSE41-LABEL: min_le_v4i32c:
31983198 ; SSE41: # BB#0:
31993199 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
32003200 ; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
32013201 ; SSE41-NEXT: retq
32023202 ;
3203 ; SSE42-LABEL: max_le_v4i32c:
3203 ; SSE42-LABEL: min_le_v4i32c:
32043204 ; SSE42: # BB#0:
32053205 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
32063206 ; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
32073207 ; SSE42-NEXT: retq
32083208 ;
3209 ; AVX-LABEL: max_le_v4i32c:
3209 ; AVX-LABEL: min_le_v4i32c:
32103210 ; AVX: # BB#0:
32113211 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
32123212 ; AVX-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
32183218 ret <4 x i32> %4
32193219 }
32203220
3221 define <8 x i32> @max_le_v8i32c() {
3222 ; SSE2-LABEL: max_le_v8i32c:
3221 define <8 x i32> @min_le_v8i32c() {
3222 ; SSE2-LABEL: min_le_v8i32c:
32233223 ; SSE2: # BB#0:
32243224 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483649,2147483651,2147483653,2147483655]
32253225 ; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
32373237 ; SSE2-NEXT: por %xmm3, %xmm1
32383238 ; SSE2-NEXT: retq
32393239 ;
3240 ; SSE41-LABEL: max_le_v8i32c:
3240 ; SSE41-LABEL: min_le_v8i32c:
32413241 ; SSE41: # BB#0:
32423242 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
32433243 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
32453245 ; SSE41-NEXT: pminud {{.*}}(%rip), %xmm1
32463246 ; SSE41-NEXT: retq
32473247 ;
3248 ; SSE42-LABEL: max_le_v8i32c:
3248 ; SSE42-LABEL: min_le_v8i32c:
32493249 ; SSE42: # BB#0:
32503250 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
32513251 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
32533253 ; SSE42-NEXT: pminud {{.*}}(%rip), %xmm1
32543254 ; SSE42-NEXT: retq
32553255 ;
3256 ; AVX1-LABEL: max_le_v8i32c:
3256 ; AVX1-LABEL: min_le_v8i32c:
32573257 ; AVX1: # BB#0:
32583258 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
32593259 ; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
32623262 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
32633263 ; AVX1-NEXT: retq
32643264 ;
3265 ; AVX2-LABEL: max_le_v8i32c:
3265 ; AVX2-LABEL: min_le_v8i32c:
32663266 ; AVX2: # BB#0:
32673267 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
32683268 ; AVX2-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
32693269 ; AVX2-NEXT: retq
32703270 ;
3271 ; AVX512-LABEL: max_le_v8i32c:
3271 ; AVX512-LABEL: min_le_v8i32c:
32723272 ; AVX512: # BB#0:
32733273 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
32743274 ; AVX512-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
32803280 ret <8 x i32> %4
32813281 }
32823282
3283 define <8 x i16> @max_le_v8i16c() {
3284 ; SSE2-LABEL: max_le_v8i16c:
3283 define <8 x i16> @min_le_v8i16c() {
3284 ; SSE2-LABEL: min_le_v8i16c:
32853285 ; SSE2: # BB#0:
32863286 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65529,65531,65533,65535,1,3,5,7]
32873287 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,65533,65531,65529,7,5,3,1]
32943294 ; SSE2-NEXT: por %xmm1, %xmm0
32953295 ; SSE2-NEXT: retq
32963296 ;
3297 ; SSE41-LABEL: max_le_v8i16c:
3297 ; SSE41-LABEL: min_le_v8i16c:
32983298 ; SSE41: # BB#0:
32993299 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
33003300 ; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
33013301 ; SSE41-NEXT: retq
33023302 ;
3303 ; SSE42-LABEL: max_le_v8i16c:
3303 ; SSE42-LABEL: min_le_v8i16c:
33043304 ; SSE42: # BB#0:
33053305 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
33063306 ; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
33073307 ; SSE42-NEXT: retq
33083308 ;
3309 ; AVX-LABEL: max_le_v8i16c:
3309 ; AVX-LABEL: min_le_v8i16c:
33103310 ; AVX: # BB#0:
33113311 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
33123312 ; AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
33183318 ret <8 x i16> %4
33193319 }
33203320
3321 define <16 x i16> @max_le_v16i16c() {
3322 ; SSE2-LABEL: max_le_v16i16c:
3321 define <16 x i16> @min_le_v16i16c() {
3322 ; SSE2-LABEL: min_le_v16i16c:
33233323 ; SSE2: # BB#0:
33243324 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65529,65530,65531,65532,65533,65534,65535,0]
33253325 ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [1,2,3,4,5,6,7,8]
33403340 ; SSE2-NEXT: por %xmm3, %xmm1
33413341 ; SSE2-NEXT: retq
33423342 ;
3343 ; SSE41-LABEL: max_le_v16i16c:
3343 ; SSE41-LABEL: min_le_v16i16c:
33443344 ; SSE41: # BB#0:
33453345 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
33463346 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
33483348 ; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm1
33493349 ; SSE41-NEXT: retq
33503350 ;
3351 ; SSE42-LABEL: max_le_v16i16c:
3351 ; SSE42-LABEL: min_le_v16i16c:
33523352 ; SSE42: # BB#0:
33533353 ; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
33543354 ; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
33563356 ; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm1
33573357 ; SSE42-NEXT: retq
33583358 ;
3359 ; AVX1-LABEL: max_le_v16i16c:
3359 ; AVX1-LABEL: min_le_v16i16c:
33603360 ; AVX1: # BB#0:
33613361 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
33623362 ; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
33653365 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
33663366 ; AVX1-NEXT: retq
33673367 ;
3368 ; AVX2-LABEL: max_le_v16i16c:
3368 ; AVX2-LABEL: min_le_v16i16c:
33693369 ; AVX2: # BB#0:
33703370 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
33713371 ; AVX2-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
33723372 ; AVX2-NEXT: retq
33733373 ;
3374 ; AVX512-LABEL: max_le_v16i16c:
3374 ; AVX512-LABEL: min_le_v16i16c:
33753375 ; AVX512: # BB#0:
33763376 ; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
33773377 ; AVX512-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
33833383 ret <16 x i16> %4
33843384 }
33853385
3386 define <16 x i8> @max_le_v16i8c() {
3387 ; SSE-LABEL: max_le_v16i8c:
3386 define <16 x i8> @min_le_v16i8c() {
3387 ; SSE-LABEL: min_le_v16i8c:
33883388 ; SSE: # BB#0:
33893389 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
33903390 ; SSE-NEXT: pminub {{.*}}(%rip), %xmm0
33913391 ; SSE-NEXT: retq
33923392 ;
3393 ; AVX-LABEL: max_le_v16i8c:
3393 ; AVX-LABEL: min_le_v16i8c:
33943394 ; AVX: # BB#0:
33953395 ; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
33963396 ; AVX-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm0