llvm.org GIT mirror llvm / 36d7c2b
Move size and alignment information of regclass to TargetRegisterInfo 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301221 91177308-0d34-0410-b5e6-96231b3b80d8 Krzysztof Parzyszek 3 years ago
47 changed file(s) with 298 addition(s) and 234 deletion(s). Raw diff Collapse all Expand all
9292 return MC->contains(Reg1, Reg2);
9393 }
9494
95 /// Return the size of the register in bytes, which is also the size
96 /// of a stack slot allocated to hold a spilled copy of this register.
97 unsigned getSize() const { return SpillSize; }
98
99 /// Return the minimum required alignment for a register of this class.
100 unsigned getAlignment() const { return SpillAlignment; }
101
10295 /// Return the cost of copying a value between two registers in this class.
10396 /// A negative number means the register class is very expensive
10497 /// to copy e.g. status flag register classes.
324317 /// This is the inverse operation of VirtReg2IndexFunctor below.
325318 static unsigned index2VirtReg(unsigned Index) {
326319 return Index | (1u << 31);
320 }
321
322 /// Return the size in bits of a register from class RC.
323 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
324 return RC.SpillSize * 8;
325 }
326
327 /// Return the size in bytes of the stack slot allocated to hold a spilled
328 /// copy of a register from class RC.
329 unsigned getSpillSize(const TargetRegisterClass &RC) const {
330 return RC.SpillSize;
331 }
332
333 /// Return the minimum required alignment for a spill slot for a register
334 /// of this class.
335 unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
336 return RC.SpillAlignment;
327337 }
328338
329339 /// Returns the Register Class of a physical register of the given type,
116116 // Otherwise, attempt to find a covering set of sub-register numbers.
117117 // For example, Q0 on ARM is a composition of D0+D1.
118118 unsigned CurPos = 0;
119 // The size of the register in bits, assuming 8 bits per byte.
120 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
119 // The size of the register in bits.
120 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
121 unsigned RegSize = TRI.getRegSizeInBits(*RC);
121122 // Keep track of the bits in the register we already emitted, so we
122123 // can avoid emitting redundant aliasing subregs.
123124 SmallBitVector Coverage(RegSize, false);
144144 }
145145 }
146146
147 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
148
147149 // Now that selection is complete, there are no more generic vregs. Verify
148150 // that the size of the now-constrained vreg is unchanged and that it has a
149151 // register class.
164166 continue;
165167
166168 if (VRegToType.second.isValid() &&
167 VRegToType.second.getSizeInBits() > (RC->getSize() * 8)) {
169 VRegToType.second.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
168170 reportGISelFailure(MF, TPC, MORE, "gisel-select",
169171 "VReg has explicit size different from class size",
170172 *MI);
4747
4848 // Verify that the Size of the register bank is big enough to cover
4949 // all the register classes it covers.
50 assert((getSize() >= SubRC.getSize() * 8) &&
50 assert(getSize() >= TRI.getRegSizeInBits(SubRC) &&
5151 "Size is not big enough for all the subclasses!");
5252 assert(covers(SubRC) && "Not all subclasses are covered");
5353 }
420420 RC = MRI.getRegClass(Reg);
421421 }
422422 assert(RC && "Unable to deduce the register class");
423 return RC->getSize() * 8;
423 return TRI.getRegSizeInBits(*RC);
424424 }
425425
426426 //------------------------------------------------------------------------------
372372 FixedSlot->Reg != Reg)
373373 ++FixedSlot;
374374
375 unsigned Size = RegInfo->getSpillSize(*RC);
375376 if (FixedSlot == FixedSpillSlots + NumFixedSpillSlots) {
376377 // Nope, just spill it anywhere convenient.
377 unsigned Align = RC->getAlignment();
378 unsigned Align = RegInfo->getSpillAlignment(*RC);
378379 unsigned StackAlign = TFI->getStackAlignment();
379380
380381 // We may not be able to satisfy the desired alignment specification of
381382 // the TargetRegisterClass if the stack alignment is smaller. Use the
382383 // min.
383384 Align = std::min(Align, StackAlign);
384 FrameIdx = MFI.CreateStackObject(RC->getSize(), Align, true);
385 FrameIdx = MFI.CreateStackObject(Size, Align, true);
385386 if ((unsigned)FrameIdx < MinCSFrameIndex) MinCSFrameIndex = FrameIdx;
386387 if ((unsigned)FrameIdx > MaxCSFrameIndex) MaxCSFrameIndex = FrameIdx;
387388 } else {
388389 // Spill it to the stack where we must.
389 FrameIdx =
390 MFI.CreateFixedSpillStackObject(RC->getSize(), FixedSlot->Offset);
390 FrameIdx = MFI.CreateFixedSpillStackObject(Size, FixedSlot->Offset);
391391 }
392392
393393 CS.setFrameIdx(FrameIdx);
211211 return SS; // Already has space allocated?
212212
213213 // Allocate a new stack object for this spill location...
214 int FrameIdx = MF->getFrameInfo().CreateSpillStackObject(RC->getSize(),
215 RC->getAlignment());
214 unsigned Size = TRI->getSpillSize(*RC);
215 unsigned Align = TRI->getSpillAlignment(*RC);
216 int FrameIdx = MF->getFrameInfo().CreateSpillStackObject(Size, Align);
216217
217218 // Assign the slot.
218219 StackSlotForVirtReg[VirtReg] = FrameIdx;
394394 // Find an available scavenging slot with size and alignment matching
395395 // the requirements of the class RC.
396396 const MachineFrameInfo &MFI = MF.getFrameInfo();
397 unsigned NeedSize = RC->getSize();
398 unsigned NeedAlign = RC->getAlignment();
397 unsigned NeedSize = TRI->getSpillSize(*RC);
398 unsigned NeedAlign = TRI->getSpillAlignment(*RC);
399399
400400 unsigned SI = Scavenged.size(), Diff = std::numeric_limits::max();
401401 int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();
160160 if (SubRegIdx)
161161 Offset = TRI->getSubRegIdxOffset(SubRegIdx);
162162
163 Locs.emplace_back(Location::Register, RC->getSize(), DwarfRegNum, Offset);
163 Locs.emplace_back(Location::Register, TRI->getSpillSize(*RC),
164 DwarfRegNum, Offset);
164165 return ++MOI;
165166 }
166167
244245 StackMaps::LiveOutReg
245246 StackMaps::createLiveOutReg(unsigned Reg, const TargetRegisterInfo *TRI) const {
246247 unsigned DwarfRegNum = getDwarfRegNum(Reg, TRI);
247 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
248 unsigned Size = TRI->getSpillSize(*TRI->getMinimalPhysRegClass(Reg));
248249 return LiveOutReg(Reg, DwarfRegNum, Size);
249250 }
250251
344344 unsigned SubIdx, unsigned &Size,
345345 unsigned &Offset,
346346 const MachineFunction &MF) const {
347 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
347348 if (!SubIdx) {
348 Size = RC->getSize();
349 Size = TRI->getSpillSize(*RC);
349350 Offset = 0;
350351 return true;
351352 }
352 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
353353 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
354354 // Convert bit size to byte size to be consistent with
355355 // MCRegisterClass::getSize().
363363 Size = BitSize /= 8;
364364 Offset = (unsigned)BitOffset / 8;
365365
366 assert(RC->getSize() >= (Offset + Size) && "bad subregister range");
366 assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
367367
368368 if (!MF.getDataLayout().isLittleEndian()) {
369 Offset = RC->getSize() - (Offset + Size);
369 Offset = TRI->getSpillSize(*RC) - (Offset + Size);
370370 }
371371 return true;
372372 }
12981298 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
12991299 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
13001300 // We want the largest possible spill size.
1301 if (SuperRC->getSize() <= BestRC->getSize())
1301 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
13021302 continue;
13031303 if (!isLegalRC(SuperRC))
13041304 continue;
264264 const TargetRegisterClass *BestRC = nullptr;
265265 unsigned *BestPreA = &PreA;
266266 unsigned *BestPreB = &PreB;
267 if (RCA->getSize() < RCB->getSize()) {
267 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
268268 std::swap(RCA, RCB);
269269 std::swap(SubA, SubB);
270270 std::swap(BestPreA, BestPreB);
272272
273273 // Also terminate the search one we have found a register class as small as
274274 // RCA.
275 unsigned MinSize = RCA->getSize();
275 unsigned MinSize = getRegSizeInBits(*RCA);
276276
277277 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
278278 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
280280 // Check if a common super-register class exists for this index pair.
281281 const TargetRegisterClass *RC =
282282 firstCommonClass(IA.getMask(), IB.getMask(), this);
283 if (!RC || RC->getSize() < MinSize)
283 if (!RC || getRegSizeInBits(*RC) < MinSize)
284284 continue;
285285
286286 // The indexes must compose identically: PreA+SubA == PreB+SubB.
289289 continue;
290290
291291 // Is RC a better candidate than BestRC?
292 if (BestRC && RC->getSize() >= BestRC->getSize())
292 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
293293 continue;
294294
295295 // Yes, RC is the smallest super-register seen so far.
298298 *BestPreB = IB.getSubReg();
299299
300300 // Bail early if we reached MinSize. We won't find a better candidate.
301 if (BestRC->getSize() == MinSize)
301 if (getRegSizeInBits(*BestRC) == MinSize)
302302 return BestRC;
303303 }
304304 }
7272 }
7373
7474 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
75 int SS = MF->getFrameInfo().CreateSpillStackObject(RC->getSize(),
76 RC->getAlignment());
75 unsigned Size = TRI->getSpillSize(*RC);
76 unsigned Align = TRI->getSpillAlignment(*RC);
77 int SS = MF->getFrameInfo().CreateSpillStackObject(Size, Align);
7778 ++NumSpillSlots;
7879 return SS;
7980 }
12021202 // If we didn't find an extra callee-saved register to spill, create
12031203 // an emergency spill slot.
12041204 if (!ExtraCSSpill || MF.getRegInfo().isPhysRegUsed(ExtraCSSpill)) {
1205 const TargetRegisterClass *RC = &AArch64::GPR64RegClass;
1206 int FI = MFI.CreateStackObject(RC->getSize(), RC->getAlignment(), false);
1205 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1206 const TargetRegisterClass &RC = AArch64::GPR64RegClass;
1207 unsigned Size = TRI->getSpillSize(RC);
1208 unsigned Align = TRI->getSpillAlignment(RC);
1209 int FI = MFI.CreateStackObject(Size, Align, false);
12071210 RS->addScavengingFrameIndex(FI);
12081211 DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI
12091212 << " as the emergency spill slot.\n");
23192319 PtrInfo, MachineMemOperand::MOStore, MFI.getObjectSize(FI), Align);
23202320 unsigned Opc = 0;
23212321 bool Offset = true;
2322 switch (RC->getSize()) {
2322 switch (TRI->getSpillSize(*RC)) {
23232323 case 1:
23242324 if (AArch64::FPR8RegClass.hasSubClassEq(RC))
23252325 Opc = AArch64::STRBui;
24232423
24242424 unsigned Opc = 0;
24252425 bool Offset = true;
2426 switch (RC->getSize()) {
2426 switch (TRI->getSpillSize(*RC)) {
24272427 case 1:
24282428 if (AArch64::FPR8RegClass.hasSubClassEq(RC))
24292429 Opc = AArch64::LDRBui;
26482648 };
26492649
26502650 if (DstMO.getSubReg() == 0 && SrcMO.getSubReg() == 0) {
2651 assert(getRegClass(DstReg)->getSize() == getRegClass(SrcReg)->getSize() &&
2651 assert(TRI.getRegSizeInBits(*getRegClass(DstReg)) ==
2652 TRI.getRegSizeInBits(*getRegClass(SrcReg)) &&
26522653 "Mismatched register size in non subreg COPY");
26532654 if (IsSpill)
26542655 storeRegToStackSlot(MBB, InsertPt, SrcReg, SrcMO.isKill(), FrameIndex,
27342735 }
27352736
27362737 if (FillRC) {
2737 assert(getRegClass(SrcReg)->getSize() == FillRC->getSize() &&
2738 assert(TRI.getRegSizeInBits(*getRegClass(SrcReg)) ==
2739 TRI.getRegSizeInBits(*FillRC) &&
27382740 "Mismatched regclass size on folded subreg COPY");
27392741 loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, FillRC, &TRI);
27402742 MachineInstr &LoadMI = *--InsertPt;
8282 const auto RC = MRI.getRegClass(Reg);
8383 auto STI = static_cast(MRI.getTargetRegisterInfo());
8484 return STI->isSGPRClass(RC) ?
85 (RC->getSize() == 4 ? SGPR32 : SGPR_TUPLE) :
86 (RC->getSize() == 4 ? VGPR32 : VGPR_TUPLE);
85 (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) :
86 (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
8787 }
8888
8989 void GCNRegPressure::inc(unsigned Reg,
468468 // this also ensures we shouldn't need a register for the offset when
469469 // emergency scavenging.
470470 int ScavengeFI = MFI.CreateFixedObject(
471 AMDGPU::SGPR_32RegClass.getSize(), 0, false);
471 TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
472472 RS->addScavengingFrameIndex(ScavengeFI);
473473 }
474474 }
16431643 const TargetRegisterClass *SuperRC,
16441644 unsigned VecReg,
16451645 int Offset) {
1646 int NumElts = SuperRC->getSize() / 4;
1646 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32;
16471647
16481648 // Skip out of bounds offsets, or else we would end up using an undefined
16491649 // register.
17921792 return LoopBB;
17931793 }
17941794
1795 static unsigned getMOVRELDPseudo(const TargetRegisterClass *VecRC) {
1796 switch (VecRC->getSize()) {
1797 case 4:
1795 static unsigned getMOVRELDPseudo(const SIRegisterInfo &TRI,
1796 const TargetRegisterClass *VecRC) {
1797 switch (TRI.getRegSizeInBits(*VecRC)) {
1798 case 32: // 4 bytes
17981799 return AMDGPU::V_MOVRELD_B32_V1;
1799 case 8:
1800 case 64: // 8 bytes
18001801 return AMDGPU::V_MOVRELD_B32_V2;
1801 case 16:
1802 case 128: // 16 bytes
18021803 return AMDGPU::V_MOVRELD_B32_V4;
1803 case 32:
1804 case 256: // 32 bytes
18041805 return AMDGPU::V_MOVRELD_B32_V8;
1805 case 64:
1806 case 512: // 64 bytes
18061807 return AMDGPU::V_MOVRELD_B32_V16;
18071808 default:
18081809 llvm_unreachable("unsupported size for MOVRELD pseudos");
18621863
18631864 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
18641865 } else {
1865 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(VecRC));
1866 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
18661867
18671868 BuildMI(MBB, I, DL, MovRelDesc)
18681869 .addReg(Dst, RegState::Define)
19061907 .addReg(PhiReg, RegState::Implicit)
19071908 .addReg(AMDGPU::M0, RegState::Implicit);
19081909 } else {
1909 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(VecRC));
1910 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
19101911
19111912 BuildMI(*LoopBB, InsPt, DL, MovRelDesc)
19121913 .addReg(Dst, RegState::Define)
427427
428428 const MachineInstr &MIA = *MI;
429429 const TargetRegisterClass *RC = TII->getOpRegClass(MIA, OpNo);
430 unsigned Size = RC->getSize();
431 Result.second = Result.first + (Size / 4);
430 unsigned Size = TRI->getRegSizeInBits(*RC);
431 Result.second = Result.first + (Size / 32);
432432
433433 return Result;
434434 }
215215
216216 // XXX - What if this is a write into a super register?
217217 const TargetRegisterClass *RC = TII->getOpRegClass(MI, 0);
218 unsigned Size = RC->getSize();
219 Result.Named.LGKM = Size > 4 ? 2 : 1;
218 unsigned Size = TRI->getRegSizeInBits(*RC);
219 Result.Named.LGKM = Size > 32 ? 2 : 1;
220220 } else {
221221 // s_dcache_inv etc. do not have a a destination register. Assume we
222222 // want a wait on these.
288288
289289 RegInterval SIInsertWaits::getRegInterval(const TargetRegisterClass *RC,
290290 const MachineOperand &Reg) const {
291 unsigned Size = RC->getSize();
292 assert(Size >= 4);
291 unsigned Size = TRI->getRegSizeInBits(*RC);
292 assert(Size >= 32);
293293
294294 RegInterval Result;
295295 Result.first = TRI->getEncodingValue(Reg.getReg());
296 Result.second = Result.first + Size / 4;
296 Result.second = Result.first + Size / 32;
297297
298298 return Result;
299299 }
249249
250250 unsigned EltSize;
251251 if (LdSt.mayLoad())
252 EltSize = getOpRegClass(LdSt, 0)->getSize() / 2;
252 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16;
253253 else {
254254 assert(LdSt.mayStore());
255255 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
256 EltSize = getOpRegClass(LdSt, Data0Idx)->getSize();
256 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8;
257257 }
258258
259259 if (isStride64(Opc))
349349 FirstLdSt.getParent()->getParent()->getRegInfo();
350350 const TargetRegisterClass *DstRC = MRI.getRegClass(FirstDst->getReg());
351351
352 return (NumLoads * DstRC->getSize()) <= LoadClusterThreshold;
352 return (NumLoads * (RI.getRegSizeInBits(*DstRC) / 8)) <= LoadClusterThreshold;
353353 }
354354
355355 static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB,
437437 unsigned EltSize = 4;
438438 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
439439 if (RI.isSGPRClass(RC)) {
440 if (RC->getSize() > 4) {
440 if (RI.getRegSizeInBits(*RC) > 32) {
441441 Opcode = AMDGPU::S_MOV_B64;
442442 EltSize = 8;
443443 } else {
497497
498498 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
499499
500 if (DstRC->getSize() == 4) {
500 if (RI.getRegSizeInBits(*DstRC) == 32) {
501501 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
502 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
502 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) {
503503 return AMDGPU::S_MOV_B64;
504 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
504 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) {
505505 return AMDGPU::V_MOV_B64_PSEUDO;
506506 }
507507 return AMDGPU::COPY;
561561 MachineMemOperand *MMO
562562 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
563563 Size, Align);
564 unsigned SpillSize = TRI->getSpillSize(*RC);
564565
565566 if (RI.isSGPRClass(RC)) {
566567 MFI->setHasSpilledSGPRs();
567568
568569 // We are only allowed to create one new instruction when spilling
569570 // registers, so we need to use pseudo instruction for spilling SGPRs.
570 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(RC->getSize()));
571 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize));
571572
572573 // The SGPR spill/restore instructions only work on number sgprs, so we need
573574 // to make sure we are using the correct register class.
574 if (TargetRegisterInfo::isVirtualRegister(SrcReg) && RC->getSize() == 4) {
575 if (TargetRegisterInfo::isVirtualRegister(SrcReg) && SpillSize == 4) {
575576 MachineRegisterInfo &MRI = MF->getRegInfo();
576577 MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0RegClass);
577578 }
606607
607608 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
608609
609 unsigned Opcode = getVGPRSpillSaveOpcode(RC->getSize());
610 unsigned Opcode = getVGPRSpillSaveOpcode(SpillSize);
610611 MFI->setHasSpilledVGPRs();
611612 BuildMI(MBB, MI, DL, get(Opcode))
612613 .addReg(SrcReg, getKillRegState(isKill)) // data
664665 DebugLoc DL = MBB.findDebugLoc(MI);
665666 unsigned Align = FrameInfo.getObjectAlignment(FrameIndex);
666667 unsigned Size = FrameInfo.getObjectSize(FrameIndex);
668 unsigned SpillSize = TRI->getSpillSize(*RC);
667669
668670 MachinePointerInfo PtrInfo
669671 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
674676 if (RI.isSGPRClass(RC)) {
675677 // FIXME: Maybe this should not include a memoperand because it will be
676678 // lowered to non-memory instructions.
677 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(RC->getSize()));
678 if (TargetRegisterInfo::isVirtualRegister(DestReg) && RC->getSize() == 4) {
679 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize));
680 if (TargetRegisterInfo::isVirtualRegister(DestReg) && SpillSize == 4) {
679681 MachineRegisterInfo &MRI = MF->getRegInfo();
680682 MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0RegClass);
681683 }
705707
706708 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
707709
708 unsigned Opcode = getVGPRSpillRestoreOpcode(RC->getSize());
710 unsigned Opcode = getVGPRSpillRestoreOpcode(SpillSize);
709711 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
710712 .addFrameIndex(FrameIndex) // vaddr
711713 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
14441446
14451447 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
14461448 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
1447 unsigned DstSize = DstRC->getSize();
1448
1449 if (DstSize == 4) {
1449 unsigned DstSize = RI.getRegSizeInBits(*DstRC);
1450
1451 if (DstSize == 32) {
14501452 unsigned SelOp = Pred == SCC_TRUE ?
14511453 AMDGPU::S_CSELECT_B32 : AMDGPU::V_CNDMASK_B32_e32;
14521454
14601462 return;
14611463 }
14621464
1463 if (DstSize == 8 && Pred == SCC_TRUE) {
1465 if (DstSize == 64 && Pred == SCC_TRUE) {
14641466 MachineInstr *Select =
14651467 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), DstReg)
14661468 .addReg(FalseReg)
14871489 unsigned SelOp = AMDGPU::V_CNDMASK_B32_e32;
14881490 const TargetRegisterClass *EltRC = &AMDGPU::VGPR_32RegClass;
14891491 const int16_t *SubIndices = Sub0_15;
1490 int NElts = DstSize / 4;
1492 int NElts = DstSize / 32;
14911493
14921494 // 64-bit select is only avaialble for SALU.
14931495 if (Pred == SCC_TRUE) {
27462748 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
27472749 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC);
27482750 unsigned DstReg = MRI.createVirtualRegister(SRC);
2749 unsigned SubRegs = VRC->getSize() / 4;
2751 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32;
27502752
27512753 SmallVector SRegs;
27522754 for (unsigned i = 0; i < SubRegs; ++i) {
625625 return 4;
626626 }
627627
628 return RI.getRegClass(OpInfo.RegClass)->getSize();
628 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
629629 }
630630
631631 /// \brief This form should usually be preferred since it handles operands
632632 /// with unknown register classes.
633633 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
634 return getOpRegClass(MI, OpNo)->getSize();
634 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
635635 }
636636
637637 /// \returns true if it is legal for the operand at index \p OpNo
614614 if (SpillToSMEM && isSGPRClass(RC)) {
615615 // XXX - if private_element_size is larger than 4 it might be useful to be
616616 // able to spill wider vmem spills.
617 std::tie(EltSize, ScalarStoreOp) = getSpillEltSize(RC->getSize(), true);
617 std::tie(EltSize, ScalarStoreOp) =
618 getSpillEltSize(getRegSizeInBits(*RC) / 8, true);
618619 }
619620
620621 ArrayRef SplitParts = getRegSplitParts(RC, EltSize);
774775 if (SpillToSMEM && isSGPRClass(RC)) {
775776 // XXX - if private_element_size is larger than 4 it might be useful to be
776777 // able to spill wider vmem spills.
777 std::tie(EltSize, ScalarLoadOp) = getSpillEltSize(RC->getSize(), false);
778 std::tie(EltSize, ScalarLoadOp) =
779 getSpillEltSize(getRegSizeInBits(*RC) / 8, false);
778780 }
779781
780782 ArrayRef SplitParts = getRegSplitParts(RC, EltSize);
10371039 // TODO: It might be helpful to have some target specific flags in
10381040 // TargetRegisterClass to mark which classes are VGPRs to make this trivial.
10391041 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
1040 switch (RC->getSize()) {
1041 case 0: return false;
1042 case 1: return false;
1043 case 4:
1042 unsigned Size = getRegSizeInBits(*RC);
1043 if (Size < 32)
1044 return false;
1045 switch (Size) {
1046 case 32:
10441047 return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) != nullptr;
1045 case 8:
1048 case 64:
10461049 return getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) != nullptr;
1047 case 12:
1050 case 96:
10481051 return getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) != nullptr;
1049 case 16:
1052 case 128:
10501053 return getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) != nullptr;
1051 case 32:
1054 case 256:
10521055 return getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) != nullptr;
1053 case 64:
1056 case 512:
10541057 return getCommonSubClass(&AMDGPU::VReg_512RegClass, RC) != nullptr;
10551058 default:
10561059 llvm_unreachable("Invalid register class size");
10591062
10601063 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
10611064 const TargetRegisterClass *SRC) const {
1062 switch (SRC->getSize()) {
1063 case 4:
1065 switch (getRegSizeInBits(*SRC)) {
1066 case 32:
10641067 return &AMDGPU::VGPR_32RegClass;
1065 case 8:
1068 case 64:
10661069 return &AMDGPU::VReg_64RegClass;
1067 case 12:
1070 case 96:
10681071 return &AMDGPU::VReg_96RegClass;
1069 case 16:
1072 case 128:
10701073 return &AMDGPU::VReg_128RegClass;
1071 case 32:
1074 case 256:
10721075 return &AMDGPU::VReg_256RegClass;
1073 case 64:
1076 case 512:
10741077 return &AMDGPU::VReg_512RegClass;
10751078 default:
10761079 llvm_unreachable("Invalid register class size");
10791082
10801083 const TargetRegisterClass *SIRegisterInfo::getEquivalentSGPRClass(
10811084 const TargetRegisterClass *VRC) const {
1082 switch (VRC->getSize()) {
1083 case 4:
1085 switch (getRegSizeInBits(*VRC)) {
1086 case 32:
10841087 return &AMDGPU::SGPR_32RegClass;
1085 case 8:
1088 case 64:
10861089 return &AMDGPU::SReg_64RegClass;
1087 case 16:
1090 case 128:
10881091 return &AMDGPU::SReg_128RegClass;
1089 case 32:
1092 case 256:
10901093 return &AMDGPU::SReg_256RegClass;
1091 case 64:
1094 case 512:
10921095 return &AMDGPU::SReg_512RegClass;
10931096 default:
10941097 llvm_unreachable("Invalid register class size");
13531356 const TargetRegisterClass *DstRC,
13541357 unsigned DstSubReg,
13551358 const TargetRegisterClass *NewRC) const {
1356 unsigned SrcSize = SrcRC->getSize();
1357 unsigned DstSize = DstRC->getSize();
1358 unsigned NewSize = NewRC->getSize();
1359 unsigned SrcSize = getRegSizeInBits(*SrcRC);
1360 unsigned DstSize = getRegSizeInBits(*DstRC);
1361 unsigned NewSize = getRegSizeInBits(*NewRC);
13591362
13601363 // Do not increase size of registers beyond dword, we would need to allocate
13611364 // adjacent registers and constraint regalloc more than needed.
13621365
13631366 // Always allow dword coalescing.
1364 if (SrcSize <= 4 || DstSize <= 4)
1367 if (SrcSize <= 32 || DstSize <= 32)
13651368 return true;
13661369
13671370 return NewSize <= DstSize || NewSize <= SrcSize;
904904 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
905905 MFI.getObjectSize(FI), Align);
906906
907 switch (RC->getSize()) {
907 switch (TRI->getSpillSize(*RC)) {
908908 case 4:
909909 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
910910 BuildMI(MBB, I, DL, get(ARM::STRi12))
11021102 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
11031103 MFI.getObjectSize(FI), Align);
11041104
1105 switch (RC->getSize()) {
1105 switch (TRI->getSpillSize(*RC)) {
11061106 case 4:
11071107 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
11081108 BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
805805 if (!DstSubReg)
806806 return true;
807807 // Small registers don't frequently cause a problem, so we can coalesce them.
808 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
808 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
809 getRegSizeInBits(*SrcRC) < 256)
809810 return true;
810811
811812 auto NewRCWeight =
19591959 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
19601960 // closest to SP or frame pointer.
19611961 assert(RS && "Register scavenging not provided");
1962 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1963 RS->addScavengingFrameIndex(MFI.CreateStackObject(RC->getSize(),
1964 RC->getAlignment(),
1965 false));
1962 const TargetRegisterClass &RC = ARM::GPRRegClass;
1963 unsigned Size = TRI->getSpillSize(RC);
1964 unsigned Align = TRI->getSpillAlignment(RC);
1965 RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
19661966 }
19671967 }
19681968 }
111111 const AVRSubtarget &STI = MF->getSubtarget();
112112 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
113113
114 unsigned BytesPerReg = TRI.getMinimalPhysRegClass(Reg)->getSize();
114 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
115 unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8;
115116 assert(BytesPerReg <= 2 && "Only 8 and 16 bit regs are supported.");
116117
117118 unsigned RegIdx = ByteNumber / BytesPerReg;
238238 unsigned Reg = CSI[i - 1].getReg();
239239 bool IsNotLiveIn = !MBB.isLiveIn(Reg);
240240
241 assert(TRI->getMinimalPhysRegClass(Reg)->getSize() == 1 &&
241 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
242242 "Invalid register size");
243243
244244 // Add the callee-saved register as live-in only if it is not already a
276276 for (const CalleeSavedInfo &CCSI : CSI) {
277277 unsigned Reg = CCSI.getReg();
278278
279 assert(TRI->getMinimalPhysRegClass(Reg)->getSize() == 1 &&
279 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
280280 "Invalid register size");
281281
282282 BuildMI(MBB, MI, DL, TII.get(AVR::POPRd), Reg);
346346
347347 unsigned PhysS = (RR.Sub == 0) ? PhysR : TRI.getSubReg(PhysR, RR.Sub);
348348 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PhysS);
349 uint16_t BW = RC->getSize()*8;
349 uint16_t BW = TRI.getRegSizeInBits(*RC);
350350 return BW;
351351 }
352352
285285 const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
286286 const MachineFunction &MF = *MI.getParent()->getParent();
287287 const auto &HST = MF.getSubtarget();
288 unsigned VectorSize = HST.useHVXSglOps()
289 ? Hexagon::VectorRegsRegClass.getSize()
290 : Hexagon::VectorRegs128BRegClass.getSize();
288 const auto &VecRC = HST.useHVXSglOps() ? Hexagon::VectorRegsRegClass
289 : Hexagon::VectorRegs128BRegClass;
290 unsigned VectorSize = HST.getRegisterInfo()->getSpillSize(VecRC);
291291
292292 switch (Inst.getOpcode()) {
293293 default: return;
406406 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg);
407407 if (RR.Sub == 0) {
408408 Begin = 0;
409 Width = RC->getSize()*8;
409 Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC);
410410 return true;
411411 }
412412
416416 case Hexagon::DoubleRegsRegClassID:
417417 case Hexagon::VecDblRegsRegClassID:
418418 case Hexagon::VecDblRegs128BRegClassID:
419 Width = RC->getSize()*8 / 2;
419 Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 2;
420420 if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi)
421421 Begin = Width;
422422 break;
10531053 class RedundantInstrElimination : public Transformation {
10541054 public:
10551055 RedundantInstrElimination(BitTracker &bt, const HexagonInstrInfo &hii,
1056 MachineRegisterInfo &mri)
1057 : Transformation(true), HII(hii), MRI(mri), BT(bt) {}
1056 const HexagonRegisterInfo &hri, MachineRegisterInfo &mri)
1057 : Transformation(true), HII(hii), HRI(hri), MRI(mri), BT(bt) {}
10581058
10591059 bool processBlock(MachineBasicBlock &B, const RegisterSet &AVs) override;
10601060
10691069 bool usedBitsEqual(BitTracker::RegisterRef RD, BitTracker::RegisterRef RS);
10701070
10711071 const HexagonInstrInfo &HII;
1072 const HexagonRegisterInfo &HRI;
10721073 MachineRegisterInfo &MRI;
10731074 BitTracker &BT;
10741075 };
12611262 assert(MI.getOperand(OpN).isReg());
12621263 BitTracker::RegisterRef RR = MI.getOperand(OpN);
12631264 const TargetRegisterClass *RC = HBS::getFinalVRegClass(RR, MRI);
1264 uint16_t Width = RC->getSize()*8;
1265 uint16_t Width = HRI.getRegSizeInBits(*RC);
12651266
12661267 if (!GotBits)
12671268 T.set(Begin, Begin+Width);
26502651 Changed |= visitBlock(Entry, ImmG, AIG);
26512652
26522653 RegisterSet ARE; // Available registers for RIE.
2653 RedundantInstrElimination RIE(BT, HII, MRI);
2654 RedundantInstrElimination RIE(BT, HII, HRI, MRI);
26542655 bool Ried = visitBlock(Entry, RIE, ARE);
26552656 if (Ried) {
26562657 Changed = true;
558558 }
559559 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
560560 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
561 switch (RC->getSize()) {
562 case 4:
561 switch (TRI->getRegSizeInBits(*RC)) {
562 case 32:
563563 return IfTrue ? A2_tfrt : A2_tfrf;
564 case 8:
564 case 64:
565565 return IfTrue ? A2_tfrpt : A2_tfrpf;
566566 }
567567 llvm_unreachable("Invalid register operand");
14241424 if (!SRegs[S->Reg])
14251425 continue;
14261426 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1427 int FI = MFI.CreateFixedSpillStackObject(RC->getSize(), S->Offset);
1427 int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset);
14281428 MinOffset = std::min(MinOffset, S->Offset);
14291429 CSI.push_back(CalleeSavedInfo(S->Reg, FI));
14301430 SRegs[S->Reg] = false;
14361436 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
14371437 unsigned R = x;
14381438 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
1439 int Off = MinOffset - RC->getSize();
1440 unsigned Align = std::min(RC->getAlignment(), getStackAlignment());
1439 unsigned Size = TRI->getSpillSize(*RC);
1440 int Off = MinOffset - Size;
1441 unsigned Align = std::min(TRI->getSpillAlignment(*RC), getStackAlignment());
14411442 assert(isPowerOf2_32(Align));
14421443 Off &= -Align;
1443 int FI = MFI.CreateFixedSpillStackObject(RC->getSize(), Off);
1444 int FI = MFI.CreateFixedSpillStackObject(Size, Off);
14441445 MinOffset = std::min(MinOffset, Off);
14451446 CSI.push_back(CalleeSavedInfo(R, FI));
14461447 SRegs[R] = false;
16761677 int FI = MI->getOperand(0).getIndex();
16771678
16781679 bool Is128B = HST.useHVXDblOps();
1679 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1680 : &Hexagon::VectorRegs128BRegClass;
1681 unsigned Size = RC->getSize();
1682 unsigned NeedAlign = RC->getAlignment();
1680 const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass
1681 : Hexagon::VectorRegs128BRegClass;
1682 unsigned Size = HRI.getSpillSize(RC);
1683 unsigned NeedAlign = HRI.getSpillAlignment(RC);
16831684 unsigned HasAlign = MFI.getObjectAlignment(FI);
16841685 unsigned StoreOpc;
16851686
17331734 int FI = MI->getOperand(1).getIndex();
17341735
17351736 bool Is128B = HST.useHVXDblOps();
1736 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1737 : &Hexagon::VectorRegs128BRegClass;
1738 unsigned Size = RC->getSize();
1739 unsigned NeedAlign = RC->getAlignment();
1737 const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass
1738 : Hexagon::VectorRegs128BRegClass;
1739 unsigned Size = HRI.getSpillSize(RC);
1740 unsigned NeedAlign = HRI.getSpillAlignment(RC);
17401741 unsigned HasAlign = MFI.getObjectAlignment(FI);
17411742 unsigned LoadOpc;
17421743
17761777 if (!MI->getOperand(0).isFI())
17771778 return false;
17781779
1780 auto &HRI = *HST.getRegisterInfo();
17791781 DebugLoc DL = MI->getDebugLoc();
17801782 unsigned SrcR = MI->getOperand(2).getReg();
17811783 bool IsKill = MI->getOperand(2).isKill();
17821784 int FI = MI->getOperand(0).getIndex();
17831785
17841786 bool Is128B = HST.useHVXDblOps();
1785 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1786 : &Hexagon::VectorRegs128BRegClass;
1787
1788 unsigned NeedAlign = RC->getAlignment();
1787 const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass
1788 : Hexagon::VectorRegs128BRegClass;
1789 unsigned NeedAlign = HRI.getSpillAlignment(RC);
17891790 unsigned HasAlign = MFI.getObjectAlignment(FI);
17901791 unsigned StoreOpc;
17911792
18141815 if (!MI->getOperand(1).isFI())
18151816 return false;
18161817
1818 auto &HRI = *HST.getRegisterInfo();
18171819 DebugLoc DL = MI->getDebugLoc();
18181820 unsigned DstR = MI->getOperand(0).getReg();
18191821 int FI = MI->getOperand(1).getIndex();
18201822
18211823 bool Is128B = HST.useHVXDblOps();
1822 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
1823 : &Hexagon::VectorRegs128BRegClass;
1824
1825 unsigned NeedAlign = RC->getAlignment();
1824 const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass
1825 : Hexagon::VectorRegs128BRegClass;
1826 unsigned NeedAlign = HRI.getSpillAlignment(RC);
18261827 unsigned HasAlign = MFI.getObjectAlignment(FI);
18271828 unsigned LoadOpc;
18281829
19311932 if (!needToReserveScavengingSpillSlots(MF, HRI, RC))
19321933 continue;
19331934 unsigned Num = RC == &Hexagon::IntRegsRegClass ? NumberScavengerSlots : 1;
1934 unsigned S = RC->getSize(), A = RC->getAlignment();
1935 unsigned S = HRI.getSpillSize(*RC), A = HRI.getSpillAlignment(*RC);
19351936 for (unsigned i = 0; i < Num; i++) {
19361937 int NewFI = MFI.CreateSpillStackObject(S, A);
19371938 RS->addScavengingFrameIndex(NewFI);
272272 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
273273 const std::vector &CSI = MFI.getCalleeSavedInfo();
274274 // size of stack area to which FP callee-saved regs are saved.
275 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
276 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
277 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
275 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;
276 unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;
277 unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;
278278 bool HasAFGR64Reg = false;
279279 unsigned CSFPRegsSize = 0;
280280
118118
119119 // Conservatively assume all callee-saved registers will be saved.
120120 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
121 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize();
121 unsigned Size = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
122122 Offset = alignTo(Offset + Size, Size);
123123 }
124124
5252 }
5353
5454 void MipsFunctionInfo::createEhDataRegsFI() {
55 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5556 for (int I = 0; I < 4; ++I) {
56 const TargetRegisterClass *RC =
57 const TargetRegisterClass &RC =
5758 static_cast(MF.getTarget()).getABI().IsN64()
58 ? &Mips::GPR64RegClass
59 : &Mips::GPR32RegClass;
59 ? Mips::GPR64RegClass
60 : Mips::GPR32RegClass;
6061
61 EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(RC->getSize(),
62 RC->getAlignment(), false);
62 EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC),
63 TRI.getSpillAlignment(RC), false);
6364 }
6465 }
6566
6869 // The current implementation only supports Mips32r2+ not Mips64rX. Status
6970 // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture,
7071 // however Mips32r2+ is the supported architecture.
71 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
72 const TargetRegisterClass &RC = Mips::GPR32RegClass;
73 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7274
7375 for (int I = 0; I < 2; ++I)
7476 ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
75 RC->getSize(), RC->getAlignment(), false);
77 TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false);
7678 }
7779
7880 bool MipsFunctionInfo::isEhDataRegFI(int FI) const {
9294 }
9395
9496 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
97 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
9598 if (MoveF64ViaSpillFI == -1) {
9699 MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject(
97 RC->getSize(), RC->getAlignment(), false);
100 TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false);
98101 }
99102 return MoveF64ViaSpillFI;
100103 }
259259 // copy dst_hi, $vr1
260260
261261 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
262 unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2;
262 const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst);
263 unsigned VRegSize = RegInfo.getRegSizeInBits(*DstRC) / 16;
263264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
264265 unsigned VR0 = MRI.createVirtualRegister(RC);
265266 unsigned VR1 = MRI.createVirtualRegister(RC);
857858 BitVector &SavedRegs,
858859 RegScavenger *RS) const {
859860 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
861 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
860862 MipsFunctionInfo *MipsFI = MF.getInfo();
861863 MipsABIInfo ABI = STI.getABI();
862864 unsigned FP = ABI.GetFramePtr();
882884 if (ExpandPseudo(MF).expand()) {
883885 // The spill slot should be half the size of the accumulator. If target is
884886 // mips64, it should be 64-bit, otherwise it should be 32-bt.
885 const TargetRegisterClass *RC = STI.hasMips64() ?
886 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
887 int FI = MF.getFrameInfo().CreateStackObject(RC->getSize(),
888 RC->getAlignment(), false);
887 const TargetRegisterClass &RC = STI.hasMips64() ?
888 Mips::GPR64RegClass : Mips::GPR32RegClass;
889 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
890 TRI->getSpillAlignment(RC),
891 false);
889892 RS->addScavengingFrameIndex(FI);
890893 }
891894
896899 if (isInt<16>(MaxSPOffset))
897900 return;
898901
899 const TargetRegisterClass *RC =
900 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
901 int FI = MF.getFrameInfo().CreateStackObject(RC->getSize(),
902 RC->getAlignment(), false);
902 const TargetRegisterClass &RC =
903 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass;
904 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
905 TRI->getSpillAlignment(RC),
906 false);
903907 RS->addScavengingFrameIndex(FI);
904908 }
905909
566566 const MCInstrDesc &Desc = get(Opc);
567567 assert(Desc.NumOperands == 2 && "Unary instruction expected.");
568568 const MipsRegisterInfo *RI = &getRegisterInfo();
569 unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
570 unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
569 unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
570 unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));
571571
572572 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
573573 }
3737 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
3838 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
3939
40 if (DestRC->getSize() != SrcRC->getSize())
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))
4141 report_fatal_error("Copy one register into another with a different width");
4242
4343 unsigned Op;
18971897 MachineFrameInfo &MFI = MF.getFrameInfo();
18981898 if (MFI.hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
18991899 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1900 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1901 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1902 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1903 RS->addScavengingFrameIndex(MFI.CreateStackObject(RC->getSize(),
1904 RC->getAlignment(),
1905 false));
1900 const TargetRegisterClass &GPRC = PPC::GPRCRegClass;
1901 const TargetRegisterClass &G8RC = PPC::G8RCRegClass;
1902 const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC;
1903 const TargetRegisterInfo &TRI = *Subtarget.getRegisterInfo();
1904 unsigned Size = TRI.getSpillSize(RC);
1905 unsigned Align = TRI.getSpillAlignment(RC);
1906 RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
19061907
19071908 // Might we have over-aligned allocas?
19081909 bool HasAlVars = MFI.hasVarSizedObjects() &&
19101911
19111912 // These kinds of spills might need two registers.
19121913 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1913 RS->addScavengingFrameIndex(MFI.CreateStackObject(RC->getSize(),
1914 RC->getAlignment(),
1915 false));
1914 RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
19161915
19171916 }
19181917 }
11141114 return nullptr;
11151115
11161116 unsigned OpNum = Ops[0];
1117 assert(Size ==
1118 MF.getRegInfo()
1119 .getRegClass(MI.getOperand(OpNum).getReg())
1120 ->getSize() &&
1117 assert(Size * 8 ==
1118 TRI->getRegSizeInBits(*MF.getRegInfo()
1119 .getRegClass(MI.getOperand(OpNum).getReg())) &&
11211120 "Invalid size combination");
11221121
11231122 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
21482148 if (!LHSReg || !RHSReg)
21492149 return false;
21502150
2151 unsigned Opc = X86::getCMovFromCond(CC, RC->getSize());
2151 const TargetRegisterInfo &TRI = *Subtarget->getRegisterInfo();
2152 unsigned Opc = X86::getCMovFromCond(CC, TRI.getRegSizeInBits(*RC)/8);
21522153 unsigned ResultReg = fastEmitInst_rr(Opc, RC, RHSReg, RHSIsKill,
21532154 LHSReg, LHSIsKill);
21542155 updateValueMap(I, ResultReg);
19231923 continue;
19241924
19251925 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1926 unsigned Size = TRI->getSpillSize(*RC);
1927 unsigned Align = TRI->getSpillAlignment(*RC);
19261928 // ensure alignment
1927 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1929 SpillSlotOffset -= std::abs(SpillSlotOffset) % Align;
19281930 // spill into slot
1929 SpillSlotOffset -= RC->getSize();
1930 int SlotIndex =
1931 MFI.CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1931 SpillSlotOffset -= Size;
1932 int SlotIndex = MFI.CreateFixedSpillStackObject(Size, SpillSlotOffset);
19321933 CSI[i - 1].setFrameIdx(SlotIndex);
1933 MFI.ensureMaxAlignment(RC->getAlignment());
1934 MFI.ensureMaxAlignment(Align);
19341935 }
19351936
19361937 return true;
62836283 ArrayRef Cond, unsigned TrueReg,
62846284 unsigned FalseReg) const {
62856285 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
6286 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
6287 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
62866288 assert(Cond.size() == 1 && "Invalid Cond array");
62876289 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
6288 MRI.getRegClass(DstReg)->getSize(),
6290 TRI.getRegSizeInBits(RC) / 8,
62896291 false /*HasMemoryOperand*/);
62906292 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
62916293 }
65566558 bool HasAVX512 = STI.hasAVX512();
65576559 bool HasVLX = STI.hasVLX();
65586560
6559 switch (RC->getSize()) {
6561 switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
65606562 default:
65616563 llvm_unreachable("Unknown spill size");
65626564 case 1:
67166718 const TargetRegisterClass *RC,
67176719 const TargetRegisterInfo *TRI) const {
67186720 const MachineFunction &MF = *MBB.getParent();
6719 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= RC->getSize() &&
6721 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
67206722 "Stack slot too small for store");
6721 unsigned Alignment = std::max(RC->getSize(), 16);
6723 unsigned Alignment = std::max(TRI->getSpillSize(*RC), 16);
67226724 bool isAligned =
67236725 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
67246726 RI.canRealignStack(MF);
67356737 MachineInstr::mmo_iterator MMOBegin,
67366738 MachineInstr::mmo_iterator MMOEnd,
67376739 SmallVectorImpl &NewMIs) const {
6738 unsigned Alignment = std::max(RC->getSize(), 16);
6740 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6741 unsigned Alignment = std::max(TRI.getSpillSize(*RC), 16);
67396742 bool isAligned = MMOBegin != MMOEnd &&
67406743 (*MMOBegin)->getAlignment() >= Alignment;
67416744 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
67556758 const TargetRegisterClass *RC,
67566759 const TargetRegisterInfo *TRI) const {
67576760 const MachineFunction &MF = *MBB.getParent();
6758 unsigned Alignment = std::max(RC->getSize(), 16);
6761 unsigned Alignment = std::max(TRI->getSpillSize(*RC), 16);
67596762 bool isAligned =
67606763 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
67616764 RI.canRealignStack(MF);
67706773 MachineInstr::mmo_iterator MMOBegin,
67716774 MachineInstr::mmo_iterator MMOEnd,
67726775 SmallVectorImpl &NewMIs) const {
6773 unsigned Alignment = std::max(RC->getSize(), 16);
6776 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6777 unsigned Alignment = std::max(TRI.getSpillSize(*RC), 16);
67746778 bool isAligned = MMOBegin != MMOEnd &&
67756779 (*MMOBegin)->getAlignment() >= Alignment;
67766780 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
72297233 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
72307234 else {
72317235 unsigned DstReg = Instr.getOperand(0).getReg();
7232 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
7236 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
7237 NewOpc = getCMovFromCond(NewCC, TRI->getRegSizeInBits(*DstRC)/8,
72337238 HasMemoryOperand);
72347239 }
72357240
77577762 unsigned DstIdx = (Imm >> 4) & 3;
77587763 unsigned SrcIdx = (Imm >> 6) & 3;
77597764
7760 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
7765 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7766 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
7767 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
77617768 if (Size <= RCSize && 4 <= Align) {
77627769 int PtrOffset = SrcIdx * 4;
77637770 unsigned NewImm = (DstIdx << 4) | ZMask;
77797786 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
77807787 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
77817788 if (OpNum == 2) {
7782 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
7789 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7790 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
7791 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
77837792 if (Size <= RCSize && 8 <= Align) {
77847793 unsigned NewOpCode =
77857794 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
78687877 return nullptr;
78697878 bool NarrowToMOV32rm = false;
78707879 if (Size) {
7871 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
7880 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7881 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
7882 &RI, MF);
7883 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
78727884 if (Size < RCSize) {
78737885 // Check if it's safe to fold the load. If the size of the object is
78747886 // narrower than the load width, then it's not.
83098321 const MachineFunction &MF) {
83108322 unsigned Opc = LoadMI.getOpcode();
83118323 unsigned UserOpc = UserMI.getOpcode();
8312 unsigned RegSize =
8313 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
8324 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8325 const TargetRegisterClass *RC =
8326 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
8327 unsigned RegSize = TRI.getRegSizeInBits(*RC);
83148328
83158329 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
8316 RegSize > 4) {
8330 RegSize > 32) {
83178331 // These instructions only load 32 bits, we can't fold them if the
83188332 // destination register is wider than 32 bits (4 bytes), and its user
83198333 // instruction isn't scalar (SS).
83648378 }
83658379
83668380 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
8367 RegSize > 8) {
8381 RegSize > 64) {
83688382 // These instructions only load 64 bits, we can't fold them if the
83698383 // destination register is wider than 64 bits (8 bytes), and its user
83708384 // instruction isn't scalar (SD).
87098723 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
87108724 const MCInstrDesc &MCID = get(Opc);
87118725 MachineFunction &MF = DAG.getMachineFunction();
8726 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
87128727 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
87138728 unsigned NumDefs = MCID.NumDefs;
87148729 std::vector AddrOps;
87438758 return false;
87448759 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
87458760 // memory access is slow above.
8746 unsigned Alignment = std::max(RC->getSize(), 16);
8761 unsigned Alignment = std::max(TRI.getSpillSize(*RC), 16);
87478762 bool isAligned = (*MMOs.first) &&
87488763 (*MMOs.first)->getAlignment() >= Alignment;
87498764 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
87888803 return false;
87898804 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
87908805 // memory access is slow above.
8791 unsigned Alignment = std::max(RC->getSize(), 16);
8806 unsigned Alignment = std::max(TRI.getSpillSize(*RC), 16);
87928807 bool isAligned = (*MMOs.first) &&
87938808 (*MMOs.first)->getAlignment() >= Alignment;
87948809 SDNode *Store =
136136 case X86::FR32RegClassID:
137137 case X86::FR64RegClassID:
138138 // If AVX-512 isn't supported we should only inflate to these classes.
139 if (!Subtarget.hasAVX512() && Super->getSize() == RC->getSize())
139 if (!Subtarget.hasAVX512() &&
140 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
140141 return Super;
141142 break;
142143 case X86::VR128RegClassID:
143144 case X86::VR256RegClassID:
144145 // If VLX isn't supported we should only inflate to these classes.
145 if (!Subtarget.hasVLX() && Super->getSize() == RC->getSize())
146 if (!Subtarget.hasVLX() &&
147 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
146148 return Super;
147149 break;
148150 case X86::VR128XRegClassID:
149151 case X86::VR256XRegClassID:
150152 // If VLX isn't support we shouldn't inflate to these classes.
151 if (Subtarget.hasVLX() && Super->getSize() == RC->getSize())
153 if (Subtarget.hasVLX() &&
154 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
152155 return Super;
153156 break;
154157 case X86::FR32XRegClassID:
155158 case X86::FR64XRegClassID:
156159 // If AVX-512 isn't support we shouldn't inflate to these classes.
157 if (Subtarget.hasAVX512() && Super->getSize() == RC->getSize())
160 if (Subtarget.hasAVX512() &&
161 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
158162 return Super;
159163 break;
160164 case X86::GR8RegClassID:
167171 case X86::VR512RegClassID:
168172 // Don't return a super-class that would shrink the spill size.
169173 // That can happen with the vector and float classes.
170 if (Super->getSize() == RC->getSize())
174 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
171175 return Super;
172176 }
173177 Super = *I++;
574574 RegScavenger *RS) const {
575575 assert(RS && "requiresRegisterScavenging failed");
576576 MachineFrameInfo &MFI = MF.getFrameInfo();
577 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
577 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
578 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
578579 XCoreFunctionInfo *XFI = MF.getInfo();
579580 // Reserve slots close to SP or frame pointer for Scavenging spills.
580581 // When using SP for small frames, we don't need any scratch registers.
581582 // When using SP for large frames, we may need 2 scratch registers.
582583 // When using FP, for large or small frames, we may need 1 scratch register.
584 unsigned Size = TRI.getSpillSize(RC);
585 unsigned Align = TRI.getSpillAlignment(RC);
583586 if (XFI->isLargeFrame(MF) || hasFP(MF))
584 RS->addScavengingFrameIndex(MFI.CreateStackObject(RC->getSize(),
585 RC->getAlignment(),
586 false));
587 RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
587588 if (XFI->isLargeFrame(MF) && !hasFP(MF))
588 RS->addScavengingFrameIndex(MFI.CreateStackObject(RC->getSize(),
589 RC->getAlignment(),
590 false));
591 }
589 RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
590 }
99 #include "XCoreMachineFunctionInfo.h"
1010 #include "XCoreInstrInfo.h"
1111 #include "llvm/IR/Function.h"
12 #include "llvm/Target/TargetSubtargetInfo.h"
1213
1314 using namespace llvm;
1415
3435 if (LRSpillSlotSet) {
3536 return LRSpillSlot;
3637 }
37 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
38 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
39 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3840 MachineFrameInfo &MFI = MF.getFrameInfo();
3941 if (! MF.getFunction()->isVarArg()) {
4042 // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
41 LRSpillSlot = MFI.CreateFixedObject(RC->getSize(), 0, true);
43 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true);
4244 } else {
43 LRSpillSlot = MFI.CreateStackObject(RC->getSize(), RC->getAlignment(), true);
45 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC),
46 TRI.getSpillAlignment(RC), true);
4447 }
4548 LRSpillSlotSet = true;
4649 return LRSpillSlot;
5053 if (FPSpillSlotSet) {
5154 return FPSpillSlot;
5255 }
53 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
56 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
57 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5458 MachineFrameInfo &MFI = MF.getFrameInfo();
55 FPSpillSlot = MFI.CreateStackObject(RC->getSize(), RC->getAlignment(), true);
59 FPSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC),
60 TRI.getSpillAlignment(RC), true);
5661 FPSpillSlotSet = true;
5762 return FPSpillSlot;
5863 }
6166 if (EHSpillSlotSet) {
6267 return EHSpillSlot;
6368 }
64 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
69 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
70 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6571 MachineFrameInfo &MFI = MF.getFrameInfo();
66 EHSpillSlot[0] = MFI.CreateStackObject(RC->getSize(), RC->getAlignment(), true);
67 EHSpillSlot[1] = MFI.CreateStackObject(RC->getSize(), RC->getAlignment(), true);
72 unsigned Size = TRI.getSpillSize(RC);
73 unsigned Align = TRI.getSpillAlignment(RC);
74 EHSpillSlot[0] = MFI.CreateStackObject(Size, Align, true);
75 EHSpillSlot[1] = MFI.CreateStackObject(Size, Align, true);
6876 EHSpillSlotSet = true;
6977 return EHSpillSlot;
7078 }