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Merging r237164: ------------------------------------------------------------------------ r237164 | thomas.stellard | 2015-05-12 14:59:17 -0400 (Tue, 12 May 2015) | 10 lines R600/SI: Fix bug in VGPR spilling AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which caused the srsrc and soffset register to not be set correctly. This commit replaces the switch statement with a SITargetInfo query to make sure all spill instructions are covered. Differential Revision: http://reviews.llvm.org/D9582 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@240283 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
5 changed file(s) with 60 addition(s) and 67 deletion(s). Raw diff Collapse all Expand all
3535 DS = 1 << 17,
3636 MIMG = 1 << 18,
3737 FLAT = 1 << 19,
38 WQM = 1 << 20
38 WQM = 1 << 20,
39 VGPRSpill = 1 << 21
3940 };
4041 }
4142
3838 field bits<1> MIMG = 0;
3939 field bits<1> FLAT = 0;
4040 field bits<1> WQM = 0;
41 field bits<1> VGPRSpill = 0;
4142
4243 // These need to be kept in sync with the enum in SIInstrFlags.
4344 let TSFlags{0} = VM_CNT;
6566 let TSFlags{18} = MIMG;
6667 let TSFlags{19} = FLAT;
6768 let TSFlags{20} = WQM;
69 let TSFlags{21} = VGPRSpill;
6870
6971 // Most instructions require adjustments after selection to satisfy
7072 // operand requirements.
207207 return get(Opcode).TSFlags & SIInstrFlags::WQM;
208208 }
209209
210 bool isVGPRSpill(uint16_t Opcode) const {
211 return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
212 }
213
210214 bool isInlineConstant(const APInt &Imm) const;
211215 bool isInlineConstant(const MachineOperand &MO) const;
212216 bool isLiteralConstant(const MachineOperand &MO) const;
19851985 defm SI_SPILL_S512 : SI_SPILL_SGPR ;
19861986
19871987 multiclass SI_SPILL_VGPR {
1988 let UseNamedOperandTable = 1 in {
1988 let UseNamedOperandTable = 1, VGPRSpill = 1 in {
19891989 def _SAVE : InstSI <
19901990 (outs),
19911991 (ins vgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc,
19981998 (ins i32imm:$frame_idx, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset),
19991999 "", []
20002000 >;
2001 } // End UseNamedOperandTable = 1
2001 } // End UseNamedOperandTable = 1, VGPRSpill = 1
20022002 }
20032003
20042004 defm SI_SPILL_V32 : SI_SPILL_VGPR ;
127127 MachineInstr &MI = *I;
128128 RS.forward(I);
129129 DebugLoc DL = MI.getDebugLoc();
130 switch(MI.getOpcode()) {
131 default: break;
132 case AMDGPU::SI_SPILL_V512_SAVE:
133 case AMDGPU::SI_SPILL_V256_SAVE:
134 case AMDGPU::SI_SPILL_V128_SAVE:
135 case AMDGPU::SI_SPILL_V96_SAVE:
136 case AMDGPU::SI_SPILL_V64_SAVE:
137 case AMDGPU::SI_SPILL_V32_SAVE:
138 case AMDGPU::SI_SPILL_V32_RESTORE:
139 case AMDGPU::SI_SPILL_V64_RESTORE:
140 case AMDGPU::SI_SPILL_V128_RESTORE:
141 case AMDGPU::SI_SPILL_V256_RESTORE:
142 case AMDGPU::SI_SPILL_V512_RESTORE:
130 if (!TII->isVGPRSpill(MI.getOpcode()))
131 continue;
143132
144 // Scratch resource
145 unsigned ScratchRsrcReg =
146 RS.scavengeRegister(&AMDGPU::SReg_128RegClass, 0);
133 // Scratch resource
134 unsigned ScratchRsrcReg =
135 RS.scavengeRegister(&AMDGPU::SReg_128RegClass, 0);
147136
148 uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |
149 0xffffffff; // Size
137 uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |
138 0xffffffff; // Size
150139
151 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
152 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
153 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
154 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
140 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
141 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
142 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
143 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
155144
156 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc0)
157 .addExternalSymbol("SCRATCH_RSRC_DWORD0")
158 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
145 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc0)
146 .addExternalSymbol("SCRATCH_RSRC_DWORD0")
147 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
159148
160 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc1)
161 .addExternalSymbol("SCRATCH_RSRC_DWORD1")
162 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
149 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc1)
150 .addExternalSymbol("SCRATCH_RSRC_DWORD1")
151 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
163152
164 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc2)
165 .addImm(Rsrc & 0xffffffff)
166 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
153 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc2)
154 .addImm(Rsrc & 0xffffffff)
155 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
167156
168 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc3)
169 .addImm(Rsrc >> 32)
170 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
157 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc3)
158 .addImm(Rsrc >> 32)
159 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
171160
172 // Scratch Offset
173 if (ScratchOffsetReg == AMDGPU::NoRegister) {
174 ScratchOffsetReg = RS.scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
175 BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_SPILL_S32_RESTORE),
176 ScratchOffsetReg)
177 .addFrameIndex(ScratchOffsetFI)
178 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
179 .addReg(AMDGPU::SGPR0, RegState::Undef);
180 } else if (!MBB.isLiveIn(ScratchOffsetReg)) {
181 MBB.addLiveIn(ScratchOffsetReg);
182 }
161 // Scratch Offset
162 if (ScratchOffsetReg == AMDGPU::NoRegister) {
163 ScratchOffsetReg = RS.scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
164 BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_SPILL_S32_RESTORE),
165 ScratchOffsetReg)
166 .addFrameIndex(ScratchOffsetFI)
167 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
168 .addReg(AMDGPU::SGPR0, RegState::Undef);
169 } else if (!MBB.isLiveIn(ScratchOffsetReg)) {
170 MBB.addLiveIn(ScratchOffsetReg);
171 }
183172
184 if (ScratchRsrcReg == AMDGPU::NoRegister ||
185 ScratchOffsetReg == AMDGPU::NoRegister) {
186 LLVMContext &Ctx = MF.getFunction()->getContext();
187 Ctx.emitError("ran out of SGPRs for spilling VGPRs");
188 ScratchRsrcReg = AMDGPU::SGPR0;
189 ScratchOffsetReg = AMDGPU::SGPR0;
190 }
191 MI.getOperand(2).setReg(ScratchRsrcReg);
192 MI.getOperand(2).setIsKill(true);
193 MI.getOperand(2).setIsUndef(false);
194 MI.getOperand(3).setReg(ScratchOffsetReg);
195 MI.getOperand(3).setIsUndef(false);
196 MI.getOperand(3).setIsKill(false);
197 MI.addOperand(MachineOperand::CreateReg(Rsrc0, false, true, true));
198 MI.addOperand(MachineOperand::CreateReg(Rsrc1, false, true, true));
199 MI.addOperand(MachineOperand::CreateReg(Rsrc2, false, true, true));
200 MI.addOperand(MachineOperand::CreateReg(Rsrc3, false, true, true));
201
202 break;
173 if (ScratchRsrcReg == AMDGPU::NoRegister ||
174 ScratchOffsetReg == AMDGPU::NoRegister) {
175 LLVMContext &Ctx = MF.getFunction()->getContext();
176 Ctx.emitError("ran out of SGPRs for spilling VGPRs");
177 ScratchRsrcReg = AMDGPU::SGPR0;
178 ScratchOffsetReg = AMDGPU::SGPR0;
203179 }
180 MI.getOperand(2).setReg(ScratchRsrcReg);
181 MI.getOperand(2).setIsKill(true);
182 MI.getOperand(2).setIsUndef(false);
183 MI.getOperand(3).setReg(ScratchOffsetReg);
184 MI.getOperand(3).setIsUndef(false);
185 MI.getOperand(3).setIsKill(false);
186 MI.addOperand(MachineOperand::CreateReg(Rsrc0, false, true, true));
187 MI.addOperand(MachineOperand::CreateReg(Rsrc1, false, true, true));
188 MI.addOperand(MachineOperand::CreateReg(Rsrc2, false, true, true));
189 MI.addOperand(MachineOperand::CreateReg(Rsrc3, false, true, true));
204190 }
205191 }
206192 return true;