llvm.org GIT mirror llvm / 3638177
[PowerPC] NFC : Common up definitions of isIntS16Immediate and update parameter to int16_t git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307442 91177308-0d34-0410-b5e6-96231b3b80d8 Lei Huang 2 years ago
3 changed file(s) with 14 addition(s) and 30 deletion(s). Raw diff Collapse all Expand all
418418 .getNode();
419419 }
420420
421 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
422 /// or 64-bit immediate, and if the value can be accurately represented as a
423 /// sign extension from a 16-bit value. If so, this returns true and the
424 /// immediate.
425 static bool isIntS16Immediate(SDNode *N, short &Imm) {
426 if (N->getOpcode() != ISD::Constant)
427 return false;
428
429 Imm = (short)cast(N)->getZExtValue();
430 if (N->getValueType(0) == MVT::i32)
431 return Imm == (int32_t)cast(N)->getZExtValue();
432 else
433 return Imm == (int64_t)cast(N)->getZExtValue();
434 }
435
436 static bool isIntS16Immediate(SDValue Op, short &Imm) {
437 return isIntS16Immediate(Op.getNode(), Imm);
438 }
439
440421 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
441422 /// operand. If so Imm will receive the 32-bit value.
442423 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
21252106 getI32Imm(Imm & 0xFFFF, dl)), 0);
21262107 Opc = PPC::CMPLW;
21272108 } else {
2128 short SImm;
2109 int16_t SImm;
21292110 if (isIntS16Immediate(RHS, SImm))
21302111 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
21312112 getI32Imm((int)SImm & 0xFFFF,
21722153 getI64Imm(Imm & 0xFFFF, dl)), 0);
21732154 Opc = PPC::CMPLD;
21742155 } else {
2175 short SImm;
2156 int16_t SImm;
21762157 if (isIntS16Immediate(RHS, SImm))
21772158 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
21782159 getI64Imm(SImm & 0xFFFF, dl)),
33223303 if (tryLogicOpOfCompares(N))
33233304 return;
33243305
3325 short Imm;
3306 int16_t Imm;
33263307 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
33273308 isIntS16Immediate(N->getOperand(1), Imm)) {
33283309 KnownBits LHSKnown;
33453326 break;
33463327 }
33473328 case ISD::ADD: {
3348 short Imm;
3329 int16_t Imm;
33493330 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
33503331 isIntS16Immediate(N->getOperand(1), Imm)) {
33513332 selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
20312031 /// or 64-bit immediate, and if the value can be accurately represented as a
20322032 /// sign extension from a 16-bit value. If so, this returns true and the
20332033 /// immediate.
2034 static bool isIntS16Immediate(SDNode *N, short &Imm) {
2034 bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
20352035 if (!isa(N))
20362036 return false;
20372037
2038 Imm = (short)cast(N)->getZExtValue();
2038 Imm = (int16_t)cast(N)->getZExtValue();
20392039 if (N->getValueType(0) == MVT::i32)
20402040 return Imm == (int32_t)cast(N)->getZExtValue();
20412041 else
20422042 return Imm == (int64_t)cast(N)->getZExtValue();
20432043 }
2044 static bool isIntS16Immediate(SDValue Op, short &Imm) {
2044 bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
20452045 return isIntS16Immediate(Op.getNode(), Imm);
20462046 }
20472047
20512051 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
20522052 SDValue &Index,
20532053 SelectionDAG &DAG) const {
2054 short imm = 0;
2054 int16_t imm = 0;
20552055 if (N.getOpcode() == ISD::ADD) {
20562056 if (isIntS16Immediate(N.getOperand(1), imm))
20572057 return false; // r+i
21412141 return false;
21422142
21432143 if (N.getOpcode() == ISD::ADD) {
2144 short imm = 0;
2144 int16_t imm = 0;
21452145 if (isIntS16Immediate(N.getOperand(1), imm) &&
21462146 (!Aligned || (imm & 3) == 0)) {
21472147 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
21652165 return true; // [&g+r]
21662166 }
21672167 } else if (N.getOpcode() == ISD::OR) {
2168 short imm = 0;
2168 int16_t imm = 0;
21692169 if (isIntS16Immediate(N.getOperand(1), imm) &&
21702170 (!Aligned || (imm & 3) == 0)) {
21712171 // If this is an or of disjoint bitfields, we can codegen this as an add
21932193
21942194 // If this address fits entirely in a 16-bit sext immediate field, codegen
21952195 // this as "d, 0"
2196 short Imm;
2196 int16_t Imm;
21972197 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
21982198 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
21992199 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
10951095 ISD::ArgFlagsTy &ArgFlags,
10961096 CCState &State);
10971097
1098 bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1099 bool isIntS16Immediate(SDValue Op, int16_t &Imm);
1100
10981101 } // end namespace llvm
10991102
11001103 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H