llvm.org GIT mirror llvm / 36230cd
Make requiresRegisterScavenging determination on a per MachineFunction basis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34711 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
5 changed file(s) with 15 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
393393
394394 /// requiresRegisterScavenging - returns true if the target requires (and
395395 /// can make use of) the register scavenger.
396 virtual bool requiresRegisterScavenging() const {
396 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
397397 return false;
398398 }
399399
441441 const TargetMachine &TM = Fn.getTarget();
442442 assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
443443 const MRegisterInfo &MRI = *TM.getRegisterInfo();
444 RegScavenger *RS = MRI.requiresRegisterScavenging() ? new RegScavenger():NULL;
444 RegScavenger *RS=MRI.requiresRegisterScavenging(Fn) ? new RegScavenger():NULL;
445445
446446 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
447447 if (RS) RS->reset(BB);
325325 return Reserved;
326326 }
327327
328 bool ARMRegisterInfo::requiresRegisterScavenging() const {
329 return EnableScavenging;
328 bool
329 ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
330 const ARMFunctionInfo *AFI = MF.getInfo();
331 return EnableScavenging && !AFI->isThumbFunction();
330332 }
331333
332334 /// hasFP - Return true if the specified function should have a dedicated frame
7373
7474 BitVector getReservedRegs(const MachineFunction &MF) const;
7575
76 bool requiresRegisterScavenging() const;
76 bool requiresRegisterScavenging(const MachineFunction &MF) const;
7777
7878 bool hasFP(const MachineFunction &MF) const;
7979
162162 return THUMB_GPR_AO;
163163 if (Subtarget.useThumbBacktraces()) {
164164 if (Subtarget.isR9Reserved())
165 return RI->requiresRegisterScavenging() ? ARM_GPR_AO_8 : ARM_GPR_AO_4;
165 return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_8:ARM_GPR_AO_4;
166166 else
167 return RI->requiresRegisterScavenging() ? ARM_GPR_AO_7 : ARM_GPR_AO_3;
167 return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_7:ARM_GPR_AO_3;
168168 } else {
169169 if (Subtarget.isR9Reserved())
170 return RI->requiresRegisterScavenging() ? ARM_GPR_AO_6 : ARM_GPR_AO_2;
170 return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_6:ARM_GPR_AO_2;
171171 else
172 return RI->requiresRegisterScavenging() ? ARM_GPR_AO_5 : ARM_GPR_AO_1;
172 return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_5:ARM_GPR_AO_1;
173173 }
174174 }
175175
183183 I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
184184 else if (Subtarget.useThumbBacktraces()) {
185185 if (Subtarget.isR9Reserved()) {
186 if (RI->requiresRegisterScavenging())
186 if (RI->requiresRegisterScavenging(MF))
187187 I = ARM_GPR_AO_8 + (sizeof(ARM_GPR_AO_8)/sizeof(unsigned));
188188 else
189189 I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
190190 } else {
191 if (RI->requiresRegisterScavenging())
191 if (RI->requiresRegisterScavenging(MF))
192192 I = ARM_GPR_AO_7 + (sizeof(ARM_GPR_AO_7)/sizeof(unsigned));
193193 else
194194 I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
195195 }
196196 } else {
197197 if (Subtarget.isR9Reserved()) {
198 if (RI->requiresRegisterScavenging())
198 if (RI->requiresRegisterScavenging(MF))
199199 I = ARM_GPR_AO_6 + (sizeof(ARM_GPR_AO_6)/sizeof(unsigned));
200200 else
201201 I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
202202 } else {
203 if (RI->requiresRegisterScavenging())
203 if (RI->requiresRegisterScavenging(MF))
204204 I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
205205 else
206206 I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));